Datasheet > EM68C08CWAG-25H

EM68C08CWAG-25H

更新时间： 2022-02-26 12:34:35

品牌	Logo	应用领域
钰创 - ETRON		动态存储器双倍数据速率
页数	文件大小	规格书
63页	1336K
描述
128M x 8 bit DDRII Synchronous DRAM (SDRAM)

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数据手册

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EM68C08CWAG-25H 数据手册

EtronTech

EM68C08CWAG

Operation Mode

The following tables provide a quick reference of available DDR2 SDRAM commands, including CKE power-down

modes and bank-to-bank commands.

Table 4. Truth Table (Note (1), (2))

Command

BankActivate

State CKE_n-1CKE_nDM BA0-2 A10 A0-9, 11-13 CS# RAS# CAS# WE#

Idle⁽³⁾

Any

Row address

Single Bank Precharge

All Banks Precharge

Write

Any

Active⁽³⁾

Column

address

Write with AutoPrecharge

(A0 – A9)

Active⁽³⁾

Column

address

Read

Read and Autoprecharge

(A0 – A9)

(Extended) Mode Register Set

No-Operation

Idle

Any

Idle

OP code

Device Deselect

Refresh

SelfRefresh Entry

SelfRefresh Exit

Idle

Any

Power Down Mode Entry

Power Down Mode Exit

Data Input Mask Disable

Data Input Mask Enable⁽⁴⁾

Active

NOTE 1: V=Valid data, X=Don't Care, L=Low level, H=High level

NOTE 2: CKEn signal is input level when commands are provided.

CKEn_-1signal is input level one clock cycle before the commands are provided.

NOTE 3: These are states of bank designated by BA signal.

NOTE 4: DM can be enabled respectively.

Rev. 1.1

Apr. /2016

1...4 5 678 9 10...63

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