EtronTech
EM636327
512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)
Preliminary (12/98)
Features
Key Specifications
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Fast access time from clock: 5/5/5.5/6.5/7.5 ns
Fast clock rate: 183/166/143/125/100 MHz
Fully synchronous operation
EM636327
- 55/6/7/8/10
5.5/6/7/8/10 ns
32/36/42/48/60 ns
Clock Cycle time(min.)
tCK3
Internal pipelined architecture
Row Active time(max.)
tRAS
Dual internal banks(256K x 32-bit x 2-bank)
Programmable Mode and Special Mode registers
- CAS# Latency: 1, 2, or 3
Access time from Read command 7/8/13/18/23 ns
tAC1
tAC3
tRC
Access time from CLK(max.)
Row Cycle time(min.)
5/5/5.5/6.5/7.5 ns
48/54/63/72/90 ns
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst-Read-Single-Write
Ordering Information
Part Number
EM636327Q-10
EM636327R-10
EM636327TQ-10
EM636327JT-10
EM636327Q-8
EM636327R-8
EM636327TQ-8
EM636327JT-8
EM636327Q-7
EM636327TQ-7
EM636327Q-6
EM636327TQ-6
EM636327Q-55
EM636327TQ-55
Frequency
100MHz
100MHz
100MHz
100MHz
125MHz
125MHz
125MHz
125MHz
143MHz
143MHz
166MHz
166MHz
183MHz
183MHz
Package
QFP
- Load Color or Mask register
Burst stop function
Individual byte controlled by DQM0-3
Block write and write-per-bit capability
Auto Refresh and Self Refresh
2048 refresh cycles/32ms
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QFP (Reverse)
TQFP1.4
TQFP1.0
QFP
Single +3.3V±0.3V power supply
Interface: LVTTL
JEDEC 100-pin Plastic package
-QFP (body thickness=2.8mm)
-TQFP1.4 (body thickness=1.4mm)
-TQFP1.0 (body thickness=1.0mm)
QFP (Reverse)
TQFP1.4
TQFP1.0
QFP
TQFP1.4
QFP
TQFP1.4
QFP
TQFP1.4
Overview
The EM636327 SGRAM is a high-speed
page, with a burst termination option. An auto
precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end
of the burst sequence. The refresh functions,
either Auto or Self Refresh are easy to use. In
addition, EM636327 features the write-per-bit and
the masked block write functions.
CMOS synchronous graphics DRAM containing 16
Mbits. It is internally configured as a dual 256K x
32 DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock
signal, CLK). Each of the 256K x 32 bit banks is
organized as 1024 rows by 256 columns by 32 bits.
Read and write accesses to the SGRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in
a programmed sequence. Accesses begin with the
registration of a BankActivate command which is
then followed by a Read or Write command.
By having a programmable mode register and
special mode register, the system can choose the
most suitable modes to maximize its performance.
These devices are well suited for applications
requiring high memory bandwidth, and when
combined with special graphics functions result in
The EM636327 provides for programmable
a
device particularly well suited to high
Read or Write burst lengths of 1, 2, 4, 8, or full
performance graphics applications.
Etron Technology, Inc.
1F, No. 1, Prosperity Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C
TEL: (886)-3-5782345 FAX: (886)-3-5779001
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.