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EM638165TS-10 PDF预览

EM638165TS-10

更新时间: 2024-02-15 20:00:09
品牌 Logo 应用领域
钰创 - ETRON 动态存储器
页数 文件大小 规格书
71页 1058K
描述
4Mega x 16 Synchronous DRAM (SDRAM)

EM638165TS-10 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:compliant风险等级:5.75
Base Number Matches:1

EM638165TS-10 数据手册

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EtronTech  
EM638165  
4Mega x 16 Synchronous DRAM (SDRAM)  
Preliminary (Rev 0.6, 2/2001)  
Features  
Pin Assignment (Top View)  
Fast access time from clock: 5/6/6/6/7 ns  
Fast clock rate: 166/143/133/125/100 MHz  
Fully synchronous operation  
Internal pipelined architecture  
1M word x 16-bit x 4-bank  
Programmable Mode registers  
- CAS# Latency: 2, or 3  
- Burst Length: 1, 2, 4, 8, or full page  
- Burst Type: interleaved or linear burst  
- Burst stop function  
·
·
·
·
·
·
VDD  
DQ0  
VDDQ  
DQ1  
DQ2  
VSSQ  
DQ3  
DQ4  
VDDQ  
DQ5  
DQ6  
VSSQ  
DQ7  
VDD  
LDQM  
WE#  
CAS#  
RAS#  
CS#  
1
2
3
4
5
6
7
8
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
VSS  
DQ15  
VSSQ  
DQ14  
DQ13  
VDDQ  
DQ12  
DQ11  
VSSQ  
DQ10  
DQ9  
VDDQ  
DQ8  
VSS  
NC/RFU  
UDQM  
CLK  
CKE  
NC  
A11  
A9  
A8  
A7  
A6  
A5  
A4  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
Auto Refresh and Self Refresh  
4096 refresh cycles/64ms  
CKE power down mode  
·
·
·
·
·
·
Single +3.3V ± 0.3V power supply  
Interface: LVTTL  
54-pin 400 mil plastic TSOP II package  
BA0  
BA1  
A10/AP  
A0  
A1  
A2  
A3  
VDD  
Overview  
The EM638165 SDRAM is a high-speed CMOS  
VSS  
synchronous DRAM containing 64 Mbits. It is internally  
configured as 4 Banks of 1M word x 16 DRAM with a  
synchronous interface (all signals are registered on the  
positive edge of the clock signal, CLK). Read and write  
accesses to the SDRAM are burst oriented; accesses  
Key Specifications  
start at  
a selected location and continue for a  
EM638165  
-
6/7/7.5/8/10  
programmed number of locations in a programmed  
sequence. Accesses begin with the registration of a  
BankActivate command which is then followed by a  
Read or Write command.  
6/7/7.5/8/10 ns  
Clock Cycle time(min.)  
tCK3  
tAC3  
tRAS  
tRC  
5/5.4/5.4/6/7 ns  
42/45/45/48/50 ns  
60/63/68/70/80 ns  
Access time from CLK(max.)  
Row Active time(max.)  
The EM638165 provides for programmable Read  
or Write burst lengths of 1, 2, 4, 8, or full page, with a  
burst termination option. An auto precharge function  
may be enabled to provide a self-timed row precharge  
that is initiated at the end of the burst sequence. The  
refresh functions, either Auto or Self Refresh are easy  
to use.  
Row Cycle time(min.)  
Ordering Information  
Part Number  
EM638165TS-6  
EM638165TS-7  
EM638165TS-7.5  
EM638165TS-8  
EM638165TS-10  
Frequency  
166MHz  
143MHz  
133MHz  
125MHz  
100MHz  
Package  
TSOP II  
TSOP II  
TSOP II  
TSOP II  
TSOP II  
By having a programmable mode register, the  
system can choose the most suitable modes to  
maximize its performance. These devices are well  
suited for applications requiring high memory  
bandwidth and particularly well suited to high  
performance PC applications.  
Etron Technology, Inc.  
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.  
TEL: (886)-3-5782345  
FAX: (886)-3-5778671  
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.  

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