DATA SHEET
64M bits SDRAM
WTR (Wide Temperature Range)
EDS6416AHBH-TT (4M words × 16 bits)
Specifications
Pin Configurations
• Density: 64M bits
• Organization
/xxx indicate active low signal.
60-ball FBGA
⎯ 1M words × 16 bits × 4 banks
• Package: 60-ball FBGA
1
2
3
4
5
6
7
A
⎯ Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 3.3V ± 0.3V
• Clock frequency: 133MHz (max.)
• Four internal banks for concurrent operation
• Interface: LVTTL
• Burst lengths (BL): 1, 2, 4, 8, full page
• Burst type (BT):
⎯ Sequential (1, 2, 4, 8, full page)
⎯ Interleave (1, 2, 4, 8)
VSS DQ15
DQ0
VDD
B
C
D
DQ14 VSSQ
DQ13 VDDQ
DQ12 DQ11
VDDQ DQ1
VSSQ DQ2
DQ4
DQ3
E
F
DQ10 VSSQ
DQ9 VDDQ
VDDQ DQ5
VSSQ DQ6
• /CAS Latency (CL): 2, 3
G
DQ8
NU
NU
NU
DQ7
NU
• Precharge: auto precharge operation for each burst
access
H
J
VSS
VDD
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 4096 cycles/64ms
⎯ Average refresh period: 15.6μs
• Operating ambient temperature range
⎯ TA = –20°C to +85°C
NU UDQM
LDQM /WE
/RAS /CAS
K
L
NU
CKE
A11
A8
CLK
NU
A9
NC
BA1
A0
/CS
BA0
A10
A1
Features
M
N
P
• Single pulsed /RAS
• Burst read/write operation and burst read/single write
operation capability
A7
A6
A5
A2
• Byte control by UDQM and LDQM
• Wide temperature range
R
VSS
A4
A3
VDD
⎯ TA = –20°C to +85°C
(Top view)
A0 to A11
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
Address input
CKE
CLK
Clock enable
Clock input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
VDD
VSS
VDDQ
VSSQ
NC*1
NU*2
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
/WE
LDQM, UDQM
Input/output mask
Not usable
Notes:1. Not internally connected.
2. Don't connect. Internally connected.
Document No. E0718E20 (Ver. 2.0)
Date Published December 2005 (K) Japan
This product became EOL in April, 2007.
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2005