EBD51RD8ABFA-7A

更新时间： 2024-02-13 01:07:22

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
19页	190K
描述
512MB Registered DDR SDRAM DIMM

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EBD51RD8ABFA-7A 数据手册

EBD51RD8ABFA

Serial PD Matrix*¹

Byte No. Function described

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value

Comments

128

Number of bytes utilized by module

80H

08H

manufacturer

Total number of bytes in serial PD

256 byte

device

Memory type

07H

0DH

0BH

01H

48H

00H

04H

SDRAM DDR

Number of row address

Number of column address

Number of DIMM ranks

Module data width

72 bits

0 (+)

Module data width continuation

Voltage interface level of this assembly 0

SSTL 2.5V

DDR SDRAM cycle time, CL = X

60H

75H

70H

CL = 2.5*³

-6B

-7A, -7B

SDRAM access from clock (tAC)

-6B

0.70ns*³

-7A, -7B

75H

02H

0.75ns*³

ECC

7.8 µs

Self refresh

DIMM configuration type

Refresh rate/type

82H

Primary SDRAM width

08H

× 8

Error checking SDRAM width

× 8

SDRAM device attributes:

Minimum clock delay back-to-back

column access

01H

1 CLK

SDRAM device attributes:

0EH

04H

0CH

01H

02H

2, 4, 8

Burst length supported

SDRAM device attributes: Number of

banks on SDRAM device

SDRAM device attributes:

/CAS latency

SDRAM device attributes:

/CS latency

SDRAM device attributes:

/WE latency

2, 2.5

SDRAM module attributes

26H

C0H

Registered

± 0.2V

SDRAM device attributes: General

Minimum clock cycle time at CLX - 0.5

-6B, -7A

-7B

Maximum data access time (tAC) from

clock at CLX - 0.5

-6B

75H

A0H

CL = 2*³

70H

0.70ns*³

0.75ns*³

-7A, -7B

75H

00H

Minimum clock cycle time at CLX - 1

Maximum data access time (tAC) from

clock at CLX - 1

00H

Minimum row precharge time (tRP)

-6B

-7A, -7B

48H

50H

18ns

20ns

Preliminary Data Sheet E0376E10 (Ver. 1.0)

1 2 3 456 7 8...19

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