EBD51RD8ABFA-7A

更新时间： 2024-01-19 00:58:23

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
19页	190K
描述
512MB Registered DDR SDRAM DIMM

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数据手册

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EBD51RD8ABFA-7A 数据手册

EBD51RD8ABFA

Byte No. Function described

Minimum row active to row active

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value

Comments

12ns

delay (tRRD)

30H

-6B

-7A, -7B

3CH

48H

50H

15ns

18ns

20ns

Minimum /RAS to /CAS delay (tRCD)

-6B

-7A, -7B

Minimum active to precharge time

(tRAS)

-6B

2AH

42ns

-7A, -7B

2DH

80H

45ns

1 rank

512MB

Module rank density

Address and command setup time

before clock (tIS)

-6B

75H

90H

75H

90H

45H

0.75ns*³

0.9ns*³

-7A, -7B

Address and command hold time after

clock (tIH)

-6B

0.75ns*³

0.9ns*³

-7A, -7B

Data input setup time before clock

(tDS)

-6B

0.45ns*³

-7A, -7B

50H

45H

0.5ns*³

Data input hold time after clock (tDH)

-6B

-7A, -7B

0.45ns*³

50H

00H

0.5ns*³

36 to 40

Superset information

Active command period (tRC)

-6B

Future use

3CH

41H

60ns*³

65ns*³

-7A, -7B

Auto refresh to active/

Auto refresh command cycle (tRFC)

-6B

48H

72ns*³

-7A, -7B

4BH

30H

75ns*³

12ns*³

SDRAM tCK cycle max. (tCK max.)

Dout to DQS skew

-6B

-7A, -7B

Data hold skew (tQHS)

-6B

2DH

32H

55H

0.45ns*³

0.5ns*³

0.55ns*³

-7A, -7B

75H

00H

0.75ns*³

Future use

Initial

46 to 61

Superset information

SPD revision

Checksum for bytes 0 to 62

-6B

59H

-7A

10H

3BH

7FH

FEH

00H

-7B

64 to 65

Manufacturer’s JEDEC ID code

Elpida Memory

67 to 71

Preliminary Data Sheet E0376E10 (Ver. 1.0)

1...3 4 567 8 9...19

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