5秒后页面跳转
EBD52UC8AAFA PDF预览

EBD52UC8AAFA

更新时间: 2022-12-22 00:38:55
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率
页数 文件大小 规格书
18页 180K
描述
512MB Unbuffered DDR SDRAM DIMM

EBD52UC8AAFA 数据手册

 浏览型号EBD52UC8AAFA的Datasheet PDF文件第2页浏览型号EBD52UC8AAFA的Datasheet PDF文件第3页浏览型号EBD52UC8AAFA的Datasheet PDF文件第4页浏览型号EBD52UC8AAFA的Datasheet PDF文件第5页浏览型号EBD52UC8AAFA的Datasheet PDF文件第6页浏览型号EBD52UC8AAFA的Datasheet PDF文件第7页 
DATA SHEET  
512MB Unbuffered DDR SDRAM DIMM  
EBD52UC8AAFA (64M words × 64 bits, 2 Ranks)  
Description  
Features  
The EBD52UC8AAFA is 64M words × 64 bits, 2 ranks  
Double Data Rate (DDR) SDRAM unbuffered module,  
mounting 16 pieces of 256M bits DDR SDRAM sealed  
in TSOP package. Read and write operations are  
performed at the cross points of the CK and the /CK.  
This high-speed data transfer is realized by the 2 bits  
prefetch-pipelined architecture. Data strobe (DQS)  
both for read and write are available for high speed and  
reliable data bus design. By setting extended mode  
register, the on-chip Delay Locked Loop (DLL) can be  
set enable or disable. This module provides high  
density mounting without utilizing surface mount  
184-pin socket type dual in line memory module  
(DIMM)  
PCB height: 31.75mm  
Lead pitch: 1.27mm  
2.5V power supply  
Data rate: 266Mbps (max.)  
2.5 V (SSTL_2 compatible) I/O  
Double Data Rate architecture; two data transfers per  
clock cycle  
Bi-directional, data strobe (DQS) is transmitted  
/received with data, to be used in capturing data at  
the receiver  
technology.  
Decoupling capacitors are mounted  
beside each TSOP on the module board.  
Data inputs and outputs are synchronized with DQS  
4 internal banks for concurrent operation  
(Component)  
DQS is edge aligned with data for READs; center  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge; data  
referenced to both edges of DQS  
Auto precharge option for each burst access  
Programmable burst length: 2, 4, 8  
Programmable /CAS latency (CL): 2, 2.5  
Refresh cycles: (8192 refresh cycles /64ms)  
7.8µs maximum average periodic refresh interval  
2 variations of refresh  
Auto refresh  
Self refresh  
Document No. E0362E20 (Ver. 2.0)  
Date Published May 2003 (K) Japan  
URL: http://www.elpida.com  
This product became EOL in June, 2004.  
Elpida Memory, Inc. 2003  

与EBD52UC8AAFA相关器件

型号 品牌 描述 获取价格 数据表
EBD52UC8AAFA-6B ELPIDA 512MB Unbuffered DDR SDRAM DIMM

获取价格

EBD52UC8AAFA-7B ELPIDA 512MB Unbuffered DDR SDRAM DIMM

获取价格

EBD52UC8AARA ELPIDA 512MB DDR SDRAM SO DIMM

获取价格

EBD52UC8AARA-6B ELPIDA 512MB DDR SDRAM SO DIMM

获取价格

EBD52UC8AARA-7A ELPIDA 512MB DDR SDRAM SO DIMM

获取价格

EBD52UC8AARA-7A-E ELPIDA DDR DRAM Module, 64MX64, 0.75ns, CMOS, SODIMM-200

获取价格