Datasheet > E53NA50

E53NA50

更新时间： 2024-09-08 21:54:23

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		晶体晶体管
页数	文件大小	规格书
7页	90K
描述
N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR

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中文翻译

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数据手册

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E53NA50 数据手册

STE53NA50

N - CHANNEL ENHANCEMENT MODE

FAST POWER MOS TRANSISTOR

TYPE

V_DSS

R_DS(on)

< 0.085 Ω

I_D

STE53NA50

500 V

53 A

■

TYPICAL R_DS(on)= 0.075 Ω

HIGH CURRENT POWER MODULE

AVALANCHERUGGED TECHNOLOGY

VERY LARGE SOA - LARGE PEAK POWER

CAPABILITY

■

EASY TO MOUNT

SAME CURRENT CAPABILITY FOR THE

TWO SOURCE TERMINALS

■

EXTREMELY LOW Rth (Junction to case)

VERY LOW INTERNAL PARASITIC

INDUCTANCE

ISOTOP

■

ISOLATED PACKAGE UL RECOGNIZED

INTERNAL SCHEMATIC DIAGRAM

APPLICATIONS

■

SMPS & UPS

MOTOR CONTROL

WELDING EQUIPMENT

OUTPUT STAGE FOR PWM, ULTRASONIC

CIRCUITS

ABSOLUTE MAXIMUM RATINGS

Symbol

V_DS

Parameter

Value

500

Unit

Drain-source Voltage (V_GS= 0)

V_DGR

V_GS

I_D

500

Drain- gate Voltage (R_GS= 20 kΩ)

Gate-source Voltage

Drain Current (continuous) at T_c= 25 ^oC

Drain Current (continuous) at T_c= 100 ^oC

Drain Current (pulsed)

± 30

I_D

_DM(• )

212

P_tot

Total Dissipation at T_c= 25 ^oC

460

Derating Factor

3.68

-55 to 150

150

W/^oC

^oC

T_{st g}

T_j

Storage Temperature

Max. Operating Junction Temperature

Insulation Withhstand Voltage (AC-RMS)

V_ISO

2500

(•) Pulse width limited by safe operating area

1/7

February 1998

12 3 4 5 6 7

中文翻译

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