Datasheet > E-STLC7550TQF7

E-STLC7550TQF7

更新时间： 2024-09-17 14:50:35

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		电信电信集成电路
页数	文件大小	规格书
24页	259K
描述
56kbps DATA, MODEM-SUPPORT CIRCUIT, PQFP48, 7 X 7 MM, 1.4 MM HEIGHT, LEAD FREE, TQFP-48

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E-STLC7550TQF7 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	LFQFP, QFP48,.35SQ,20	针数：	48
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.72	数据速率：	56 Mbps
JESD-30 代码：	S-PQFP-G48	JESD-609代码：	e3/e4
长度：	7 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	48
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP48,.35SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
电源：	3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	子类别：	Modems
标称供电电压：	3 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	MODEM-SUPPORT CIRCUIT
温度等级：	COMMERCIAL	端子面层：	TIN/NICKEL PALLADIUM GOLD
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	7 mm	Base Number Matches：	1

E-STLC7550TQF7 数据手册

STLC7550

Definition and Terminology

Data Transfer Interval

Signal Data

The time during which data is transfered from DOUTand to

D^IN. This interval is 16 shift clocks provides by the chip.

This refers to the input signal and all the converted

representations through the ADC channel and the DAC

channel.

Data Mode

This refers to the data transfer. Since the device is

synchronous, the signal data words from the ADC channel

and to the DAC channel occur simultaneously.

Control Mode

Frame Sync.

This refers to the digital control data transfer into DIN and

the register read data from D^OUT. The control mode interval

occurs when requested by hardware or software.

Frame sync refers only to the falling edge of the signal which

initiates the data transfer interval. The primary frame sync

starts the Data Mode and the secondary frame sync starts

the Control Mode.

Frame Sync and Sampling The time between falling edges of successive primary frame

Period

sync signals.

ADC Channel

This term refers to all signal processing circuits between the

analog input and the digital conversion result at D^OUT.

DAC Channel

This term refers to all signal processing circuits between the

digital data word applied to D^INand the differential output

analog signal available at OUT+ and OUT-pins.

OverSampling Ratio

This term refer to the ratio between the master clock MCLK

corresponding to the oversampling frequency and the

sampling frequency FS.

Resolution

The number of bits in the input words to the DAC, and the

output words in the ADC.

Dynamic Range

The S/(N+D) with a 1kHz, -20dBr input signal and

extrapolated to full scale. Use of a small input signal reduces

the harmonic distortion components of the noise to

insignificance. Units in dB or in N^bitas explained before.

Signal-to-

(Noise+Distortion)

S/(THD+N) is the ratio of the rms of the input signal to the

rms of all other spectral components within the

measurement bandwidth (0.425 x Sampling Frequency).

Units in dB.

Crosstalk

The amount of 1kHz signal present on the output of the

grounded input channel with 1kHz 0dB signal present on the

other channel. Units in dB.

Power Supply Rejection

Ratio

PSRR. The amount of 1kHz signal present on the output of

the grounded input channel with 1kHz 200mV^PPsignal

present on the power supply.

Rev 9

21/24

1...18 19 202122 23 24

中文翻译

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