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DTA201T3G PDF预览

DTA201T3G

更新时间: 2024-11-10 00:48:27
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FS /
页数 文件大小 规格书
7页 248K
描述
Bias Resistor Transistors

DTA201T3G 数据手册

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SEMICONDUCTOR  
DTA201 ~ DTA214 /  
DTA217 / DTA223  
TECHNICAL DATA  
Bias Resistor Transistors  
PNP Silicon Surface Mount Transistors  
with Monolithic Bias Resistor Network  
This new series of digital transistors is designed to replace a single  
device and its external resistor bias network. The BRT (Bias Resistor  
Transistor) contains a single transistor with a monolithic bias network  
consisting of two resistors; a series base resistor and a base-emitter  
resistor. The BRT eliminates these individual components by  
integrating them into a single device. The use of a BRT can reduce  
both system cost and board space. The device is housed in the SOT-23  
package which is designed for low power surface mount applications.  
3
2
1
SOT-23  
PIN 3  
COLLECTOR  
(OUTPUT)  
R1  
PIN 1  
Simplifies Circuit Design  
Reduces Board Space  
BASE  
(INPUT)  
R2  
PIN 2  
EMITTER  
Reduces Component Count  
(GROUND)  
The SOT-23 package can be soldered using wave or reflow. The  
modified gull-winged leads absorb thermal stress during soldering  
eliminating the possibility of damage to the die.  
Available in 8 mm embossed tape and reel. Use the Device Number  
to order the 7 inch/3000 unit reel. Replace “T1” with “T3” in the  
Device Number to order the 13 inch/10,000 unit reel.  
We declare that the material of product compliance with RoHS requirements.  
MAXIMUM RATINGS (TA = 25 C unless otherwise noted)  
Rating  
Collector-Base Voltage  
Collector-Emitter Voltage  
Collector Current  
Symbol  
VCBO  
VCEO  
IC  
Value  
50  
Unit  
Vdc  
50  
Vdc  
100  
mAdc  
THERMAL CHARACTERISTICS  
Characteristic  
Symbol  
PD  
Max  
Unit  
mW  
Total Device Dissipation  
TA = 25 C  
Derate above 25 C  
246 (Note 1.)  
400 (Note 2.)  
1.5 (Note 1.)  
2.0 (Note 2.)  
C/W  
C/W  
C/W  
C
Thermal Resistance –  
Junction-to-Ambient  
RθJA  
508 (Note 1.)  
311 (Note 2.)  
Thermal Resistance –  
Junction-to-Lead  
RθJL  
174 (Note 1.)  
208 (Note 2.)  
Junction and Storage  
Temperature Range  
TJ, Tstg  
–55 to +150  
1. FR–4 @ Minimum Pad  
2. FR–4 @ 1.0 x 1.0 inch Pad  
2007. 12. 18  
Revision No : 0  
1/7  

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