Datasheet > DS92LV18_06

DS92LV18_06

更新时间： 2024-02-09 15:24:19

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
20页	856K
描述
18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

DS92LV18_06 数据手册

June 2006

DS92LV18

18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz

General Description

Features

n 15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376

Gbps full duplex throughput)

The DS92LV18 Serializer/Deserializer (SERDES) pair trans-

parently translates a 18–bit parallel bus into a BLVDS serial

stream with embedded clock information. This single serial

stream simplifies transferring a 18-bit, or less, bus over PCB

traces and cables by eliminating the skew problems between

parallel data and clock paths. It saves system cost by nar-

rowing data paths that in turn reduce PCB layers, cable

width, and connector size and pins.

n Independent transmitter and receiver operation with

separate clock, enable, and power down pins

n Hot plug protection (power up high impedance) and

synchronization (receiver locks to random data)

n Wide 5% reference clock frequency tolerance for easy

system design using locally-generated clocks

n Line and local loopback modes

n Robust BLVDS serial transmission across backplanes

and cables for low EMI

n No external coding required

This SERDES pair includes built-in system and device test

capability. The line loopback feature enables the user to

check the integrity of the serial data transmission paths of

the transmitter and receiver while deserializing the serial

data to parallel data at the receiver outputs. The local loop-

back feature enables the user to check the integrity of the

transceiver from the local parallel-bus side.

n Internal PLL, no external PLL components required

n Single +3.3V power supply

n Low power: 90mA (typ) transmitter, 100mA (typ) at 66

MHz with PRBS-15 pattern

The DS92LV18 incorporates modified BLVDS signaling on

the high-speed I/O. BLVDS provides a low power and low

noise environment for reliably transferring data over a serial

transmission path. The equal and opposite currents through

the differential data path control EMI by coupling the result-

ing fringing fields together.

100 mV receiver input threshold

n Loss of lock detection and reporting pin

n Industrial −40 to +85˚C temperature range

2.0kV HBM ESD

n Compact, standard 80-pin LQFP package

Block Diagram

DS92LV18

20031201

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS200312

www.national.com

12 3 4 5 6 7...20

中文翻译

下载PDF

与DS92LV18_06相关器件

型号	品牌	获取价格	描述	数据表
DS92LV18TVV	NSC	获取价格	18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz
DS92LV18TVV/NOPB	NSC	获取价格	IC LINE TRANSCEIVER, PQFP80, LQFP-80, Line Driver or Receiver
DS92LV18TVV/NOPB	TI	获取价格	18 位总线 LVDS 串行器/解串器 - 15-66MHz \| PN \| 80 \| -4
DS92LV18TVVX	NSC	获取价格	IC LINE TRANSCEIVER, PQFP80, LQFP-80, Line Driver or Receiver
DS92LV18TVVX/NOPB	TI	获取价格	18 位总线 LVDS 串行器/解串器 - 15-66MHz \| PN \| 80 \| -4
DS92LV222A	NSC	获取价格	Two Channel Bus LVDS MUXed Repeater
DS92LV222ATM	NSC	获取价格	Two Channel Bus LVDS MUXed Repeater
DS92LV222ATM/NOPB	TI	获取价格	LINE TRANSCEIVER, PDSO16, LEAD FREE, SOIC-16
DS92LV222ATM/NOPB	NSC	获取价格	IC LINE TRANSCEIVER, PDSO16, LEAD FREE, SOIC-16, Line Driver or Receiver
DS92LV222ATMX	TI	获取价格	LINE TRANSCEIVER, PDSO16, SOIC-16

产品中心

服务支持

精选活动

关于我们

帮助中心

DS92LV18_06

DS92LV18_06 数据手册

与DS92LV18_06相关器件

与DS92LV18_06相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

DS92LV18_06

DS92LV18_06 数据手册

与DS92LV18_06相关器件

与DS92LV18_06相关文章

您还可以找

您在本页遇到什么问题？