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DS92LV18TVVX/NOPB PDF预览

DS92LV18TVVX/NOPB

更新时间: 2024-09-25 11:14:31
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德州仪器 - TI /
页数 文件大小 规格书
29页 1086K
描述
18 位总线 LVDS 串行器/解串器 - 15-66MHz | PN | 80 | -40 to 85

DS92LV18TVVX/NOPB 数据手册

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DS92LV18  
www.ti.com  
SNLS156E SEPTEMBER 2003REVISED APRIL 2013  
DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz  
Check for Samples: DS92LV18  
1
FEATURES  
DESCRIPTION  
The DS92LV18 Serializer/Deserializer (SERDES) pair  
transparently translates a 18–bit parallel bus into a  
BLVDS serial stream with embedded clock  
information. This single serial stream simplifies  
transferring a 18-bit, or less, bus over PCB traces  
and cables by eliminating the skew problems  
between parallel data and clock paths. It saves  
system cost by narrowing data paths that in turn  
reduce PCB layers, cable width, and connector size  
and pins.  
2
15–66 MHz 18:1/1:18 Serializer/Deserializer  
(2.376 Gbps Full Duplex Throughput)  
Independent Transmitter and Receiver  
Operation with Separate Clock, Enable, and  
Power Down Pins  
Hot Plug Protection (Power Up High  
Impedance) and Synchronization (Receiver  
Locks to Random Data)  
Wide ±5% Reference Clock Frequency  
Tolerance for Easy System Design Using  
Locally-Generated Clocks  
This SERDES pair includes built-in system and  
device test capability. The line loopback feature  
enables the user to check the integrity of the serial  
data transmission paths of the transmitter and  
receiver while deserializing the serial data to parallel  
data at the receiver outputs. The local loopback  
feature enables the user to check the integrity of the  
transceiver from the local parallel-bus side.  
Line and Local Loopback Modes  
Robust BLVDS Serial Transmission Across  
Backplanes and Cables for Low EMI  
No External Coding Required  
Internal PLL, No External PLL Components  
Required  
The DS92LV18 incorporates modified BLVDS  
signaling on the high-speed I/O. BLVDS provides a  
low power and low noise environment for reliably  
transferring data over a serial transmission path. The  
equal and opposite currents through the differential  
data path control EMI by coupling the resulting  
fringing fields together.  
Single +3.3V Power Supply  
Low Power: 90mA (typ) Transmitter, 100mA  
(typ) at 66 MHz with PRBS-15 Pattern  
±100 mV Receiver Input Threshold  
Loss of Lock Detection and Reporting Pin  
Industrial 40 to +85°C Temperature Range  
>2.0kV HBM ESD  
Compact, Standard 80-Pin LQFP Package  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2003–2013, Texas Instruments Incorporated  

DS92LV18TVVX/NOPB 替代型号

型号 品牌 替代类型 描述 数据表
DS92LV18TVV/NOPB TI

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18 位总线 LVDS 串行器/解串器 - 15-66MHz | PN | 80 | -4

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