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DS92LV1224 PDF预览

DS92LV1224

更新时间: 2024-11-19 02:58:19
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
23页 1176K
描述
30-66 MHz 10 Bit Bus LVDS Deserializer

DS92LV1224 数据手册

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DS92LV1224  
www.ti.com  
SNLS189A APRIL 2005REVISED APRIL 2013  
DS92LV1224 30-66 MHz 10 Bit Bus LVDS Deserializer  
Check for Samples: DS92LV1224  
1
FEATURES  
DESCRIPTION  
The DS92LV1224 is a 300 to 660 Mb/s deserializer  
for high-speed unidirectional serial data transmission  
over FR-4 printed circuit board backplanes and  
balanced copper cables. It receives the Bus LVDS  
serial data stream from a compatible 10–bit serializer,  
transforms it back into a 10-bit wide parallel data bus  
and recovers parallel clock. This single serial data  
stream simplifies PCB design and reduces PCB cost  
by narrowing data paths that in turn reduce PCB size  
and number of layers. The single serial data stream  
also reduces cable size, the number of connectors,  
and eliminates clock-to-data and data-to-data skew.  
2
30–66 MHz Single 1:10 Deserializer with  
300–660 Mb/s Throughput  
Robust Bus LVDS Serial Data Transmission  
with Embedded Clock for Exceptional Noise  
Immunity and Low EMI  
Clock Recovery from PLL Lock to Random  
Data Patterns  
Ensured Transition Every Data Transfer Cycle  
Low Power Consumption < 300 mW (typ)  
at 66 MHz  
Single Differential Pair Eliminates Multi-  
Channel Skew  
The DS92LV1224 works well with Bus LVDS 10–bit  
serializers within its specified frequency operating  
range. It features low power consumption, and high  
impedance outputs in power down mode.  
Flow-Through Pinout for Easy PCB Layout  
Synchronization Mode and LOCK Indicator  
Programmable Edge Trigger on Clock  
The DS92LV1224 was designed with the flow-through  
pinout and is available in a space saving 28–lead  
SSOP package.  
High Impedance on Receiver Inputs when  
Power is Off  
Small 28-Lead SSOP Package  
Block Diagrams  
10-BIT SERIALIZER  
DS92LV1224  
LVDS  
D
D
R
I+  
10  
10  
O+  
D
R
OUT  
IN  
R
I-  
O-  
TCLK_R/F  
TCLK  
(30 MHz to 66 MHz)  
REFCLK  
REN  
TIMING and  
CONTROL  
TIMING and  
CONTROL  
PLL  
DEN  
PLL  
LOCK  
RCLK  
(30 MHz to 66 MHz)  
SYNC1  
SYNC2  
CLOCK  
RECOVERY  
RCLK_R/F  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005–2013, Texas Instruments Incorporated  

DS92LV1224 替代型号

型号 品牌 替代类型 描述 数据表
SN65LV1224B TI

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