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DS90C385MWC PDF预览

DS90C385MWC

更新时间： 2024-01-18 06:47:06
品牌 Logo 应用领域
美国国家半导体 - NSC 显示器光电二极管
页数 文件大小 规格书
17页 435K
描述
IC QUAD LINE DRIVER, UUC, WAFER, Line Driver or Receiver

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中文翻译

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DS90C385MWC 技术参数

生命周期：Obsolete包装说明：DIE, DIE OR CHIP
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.66
差分输出：YES驱动器位数：4
输入特性：STANDARD接口集成电路类型：LINE DRIVER
接口标准：EIA-644; TIA-644JESD-30 代码：X-XUUC-N
功能数量：4最高工作温度：70 °C
最低工作温度：-10 °C封装主体材料：UNSPECIFIED
封装代码：DIE封装等效代码：DIE OR CHIP
封装形状：UNSPECIFIED封装形式：UNCASED CHIP
电源：3.3 V认证状态：Not Qualified
最大接收延迟：子类别：Line Driver or Receivers
最大压摆率：60 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：NO LEAD
端子位置：UPPERBase Number Matches：1

DS90C385MWC 数据手册

 浏览型号DS90C385MWC的Datasheet PDF文件第2页浏览型号DS90C385MWC的Datasheet PDF文件第3页浏览型号DS90C385MWC的Datasheet PDF文件第4页浏览型号DS90C385MWC的Datasheet PDF文件第5页浏览型号DS90C385MWC的Datasheet PDF文件第6页浏览型号DS90C385MWC的Datasheet PDF文件第7页 
May 2003  
DS90C385/DS90C365  
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel  
Display (FPD) Link-85 MHz, +3.3V Programmable LVDS  
Transmitter 18-Bit Flat Panel Display (FPD) Link-85 MHz  
This chipset is an ideal means to solve EMI and cable size  
problems associated with wide, high-speed TTL interfaces.  
General Description  
The DS90C385 transmitter converts 28 bits of LVCMOS/  
LVTTL data into four LVDS (Low Voltage Differential Signal-  
ing) data streams. A phase-locked transmit clock is transmit-  
Features  
n 20 to 85 MHz shift clock support  
ted in parallel with the data streams over a fifth LVDS link.  
Every cycle of the transmit clock 28 bits of input data are  
sampled and transmitted. At a transmit clock frequency of 85  
MHz, 24 bits of RGB data and 3 bits of LCD timing and  
control data (FPLINE, FPFRAME, DRDY) are transmitted at  
a rate of 595 Mbps per LVDS data channel. Using a 85 MHz  
clock, the data throughput is 297.5 Mbytes/sec. Also avail-  
able is the DS90C365 that converts 21 bits of LVCMOS/  
LVTTL data into three LVDS (Low Voltage Differential Sig-  
naling) data streams. Both transmitters can be programmed  
for Rising edge strobe or Falling edge strobe through a  
dedicated pin. A Rising edge or Falling edge strobe transmit-  
ter will interoperate with a Falling edge strobe Receiver  
(DS90CF386/DS90CF366) without any translation logic.  
n Best–in–Class Set & Hold Times on TxINPUTs  
n Tx power consumption 130 mW (typ) 85MHz  
Grayscale  
<
@
<
n Tx Power-down mode 200µW (max)  
n Supports VGA, SVGA, XGA and Dual Pixel SXGA.  
n Narrow bus reduces cable size and cost  
n Up to 2.38 Gbps throughput  
n Up to 297.5 Megabytes/sec bandwidth  
n 345 mV (typ) swing LVDS devices for low EMI  
n PLL requires no external components  
n Compatible with TIA/EIA-644 LVDS standard  
n Low profile 56-lead or 48-lead TSSOP package  
n DS90C385 also available in a 64 ball, 0.8mm fine pitch  
ball grid array (FBGA) package  
The DS90C385 is also offered in a 64 ball, 0.8mm fine pitch  
ball grid array (FBGA) package which provides a 44 %  
reduction in PCB footprint compared to the TSSOP package.  
Block Diagrams  
DS90C365  
DS90C385  
10086829  
Order Number DS90C365MTD  
See NS Package Number MTD48  
10086801  
Order Number DS90C385MTD or DS90C385SLC  
See NS Package Number MTD56 or SLC64A  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2003 National Semiconductor Corporation  
DS100868  
www.national.com  
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