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DS90C387RVJD

更新时间： 2024-09-09 09:56:55

品牌	Logo	应用领域
美国国家半导体 - NSC		驱动器接口集成电路泵
页数	文件大小	规格书
28页	429K
描述
85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA

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DS90C387RVJD 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	TQFP-100	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.43	差分输出：	YES
驱动器位数：	8	输入特性：	STANDARD
接口集成电路类型：	LINE DRIVER	接口标准：	EIA-644; TIA-644
JESD-30 代码：	S-PQFP-G100	JESD-609代码：	e0
长度：	14 mm	湿度敏感等级：	3
功能数量：	8	端子数量：	100
最高工作温度：	70 °C	最低工作温度：	-10 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFQFP
封装等效代码：	TQFP100,.63SQ	封装形状：	SQUARE
封装形式：	FLATPACK, THIN PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
电源：	3.3 V	认证状态：	Not Qualified
最大接收延迟：		座面最大高度：	1.2 mm
子类别：	Line Driver or Receivers	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	14 mm

DS90C387RVJD 数据手册

December 2003

DS90C387R

85MHz Dual 12-Bit Double Pumped Input LDI Transmitter

- VGA/UXGA

and Non-DC Balanced modes. In the Non-DC Balanced

mode backward compatibility with FPD-Link Receivers is

General Description

The DS90C387R transmitter is designed to support pixel

obtained.

data transmission from a Host to a Flat Panel Display up to

This chip is an ideal solution to solve EMI and cable size

UXGA resolution. It is designed to be compatible with Graph-

problems for high-resolution flat panel display applications. It

ics Memory Controller Hub( GMCH) by implementing two

provides a reliable industry standard interface based on

data per clock and can be controlled by a two-wire serial

LVDS technology that delivers the bandwidth needed for

communication interface. Two input modes are supported:

high-resolution panels while maximizing bit times, and keep-

one port of 12-bit( two data per clock) input for 24-bit RGB,

ing clock rates low to reduce EMI and shielding require-

and two ports of 12-bit( two data per clock) input for dual

ments. For more details, please refer to the “Applications

24-bit RGB( 48-bit total). In both modes, input data will be

Information” section of this datasheet.

clocked on both rising and falling edges in LVTTL level

operation, or clocked on the cross over of differential clock

signals in the low swing operation. Each input data width will

Features

be 1/2 of clock cycle. With an input clock at 85MHz and input

data at 170Mbps, the maximum transmission rate of each

LVDS line is 595Mbps, for a aggregate throughput rate of

2.38Gbps/4.76Gbps. It converts 24/48 bits (Single/Dual

Pixel 24-bit color) of data into 4/8 LVDS (Low Voltage Differ-

ential Signaling) data streams. DS90C387R can be pro-

grammed via the two-wire serial communication interface.

The LVDS output pin-out is identical to DS90C387. Thus,

this transmitter can be paired up with DS90CF388, receiver

of the 112MHz LDI chipset or FPD-Link Receivers in non-DC

Balance mode operation which provides GUI/LCD panel/

mother board vendors a wide choice of inter-operation with

LVDS based TFT panels.

n Complies with Open LDI specification for digital display

interfaces

n 25 to 85MHz clock support

n Supports VGA through UXGA panel resolution

n Up to 4.76Gbps bandwidth in dual 24-bit RGB in-to-dual

pixel out application.

n Dual 12-bit Double Pumped Input DVO port.

n Pre-emphasis reduces cable loading effects.

n Drives long, low cost cables

n DC Balance data transmission provided by transmitter

reduces ISI distortion

n Transmitter rejects cycle-to-cycle jitter.(+/− 2ns of input

bit period)

n Support both LVTTL and low voltage level input(capable

of 1.0 to 1.8V)

DS90C387R also comes with features that can be found on

DS90C387. Cable drive is enhanced with a user selectable

pre-emphasis feature that provides additional output current

during transitions to counteract cable loading effects. DC

Balancing on a cycle-to-cycle basis is also provided to re-

Two-wire serial communication interface up to 400 KHz

n Programmable input clock and control strobe select

n Backward compatible configuration with 112MHz LDI

and FPD-Link.

n Optional second LVDS clock for backward compatibility

w/ FPD-Link Receivers

duce ISI( Inter-Symbol Interference), control signals

(

VSYNC, HSYNC, DE) are sent during blanking intervals.

With pre-emphasis and DC Balancing, a low distortion eye-

pattern is provided at the receiver end of the cable. These

enhancements allow cables 5 to 15+ meters in length to be

driven depending on media characteristic and pixel clock

speed. Pre-emphasis is available in both the DC Balanced

n Compatible with TIA/EIA-644

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS101288

www.national.com

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与DS90C387RVJD相关器件

型号	品牌	获取价格	描述	数据表
DS90C387RVJD/NOPB	TI	获取价格	85MHz 双路 12 位双泵输入 LDI 发送器 VGA/UXGA \| NEZ \| 10
DS90C387RVJDX	NSC	获取价格	暂无描述
DS90C387RVJDX/NOPB	TI	获取价格	85MHz 双路 12 位双泵输入 LDI 发送器 VGA/UXGA \| NEZ \| 10
DS90C387VJD	TI	获取价格	+3.3V 双像素 LVDS 显示接口 (LDI)-SVGA/QXGA 发送器 \| NEZ
DS90C387VJD	NSC	获取价格	Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA
DS90C387VJD/NOPB	TI	获取价格	+3.3V 双像素 LVDS 显示接口 (LDI)-SVGA/QXGA 发送器 \| NEZ
DS90C387VJDX	NSC	获取价格	IC 9 LINE DRIVER, PQFP100, TQFP-100, Line Driver or Receiver
DS90C387VJDX/NOPB	TI	获取价格	+3.3V 双像素 LVDS 显示接口 (LDI)-SVGA/QXGA 发送器 \| NEZ
DS90C401	NSC	获取价格	Dual Low Voltage Differential Signaling (LVDS) Driver
DS90C401	TI	获取价格	双路低电压差动信号驱动器

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