Datasheet > DS90C387A_06

DS90C387A_06

更新时间： 2024-02-18 05:25:19

品牌	Logo	应用领域
美国国家半导体 - NSC		光电二极管
页数	文件大小	规格书
19页	806K
描述
Dual Pixel LVDS Display Interface/FPD-Link

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DS90C387A_06 数据手册

February 2006

DS90C387A/DS90CF388A

Dual Pixel LVDS Display Interface / FPD-Link

General Description

The DS90C387A/DS90CF388A transmitter/receiver pair is

designed to support dual pixel data transmission between

Host and Flat Panel Display up to QXGA resolutions. The

transmitter converts 48 bits (Dual Pixel 24-bit color) of

CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage

Differential Signalling) data streams. At a maximum dual

pixel rate of 112MHz, LVDS data line speed is 784Mbps,

providing a total throughput of 5.7Gbps (714 Megabytes per

second).

vides a reliable interface based on LVDS technology that

delivers the bandwidth needed for high-resolution panels

while maximizing bit times, and keeping clock rates low to

reduce EMI and shielding requirements. For more details,

please refer to the “Applications Information” section of this

datasheet.

Features

n Supports SVGA through QXGA panel resolutions

n 32.5 to 112/170MHz clock support

The LDI chipset is improved over prior generations of FPD-

Link devices and offers higher bandwidth support and longer

cable drive. To increase bandwidth, the maximum pixel clock

rate is increased to 112 MHz and 8 serialized LVDS outputs

are provided. Cable drive is enhanced with a user selectable

pre-emphasis feature that provides additional output current

during transitions to counteract cable loading effects.

n Drives long, low cost cables

n Up to 5.7 Gbps bandwidth

n Pre-emphasis reduces cable loading effects

n Dual pixel architecture supports interface to GUI and

timing controller; optional single pixel transmitter inputs

support single pixel GUI interface

n Transmitter rejects cycle-to-cycle jitter

n 5V tolerant on data and control input pins

n Programmable transmitter data and control strobe select

(rising or falling edge strobe)

The DS90C387A transmitter provides a second LVDS output

clock. Both LVDS clocks are identical. This feature supports

backward compatibility with the previous generation of FPD-

Link Receivers - the second clock allows the transmitter to

interface to panels using a ’dual pixel’ configuration of two

24-bit or 18-bit FPD-Link receivers.

n Backward compatible with FPD-Link

This chipset is an ideal means to solve EMI and cable size

problems for high-resolution flat panel applications. It pro-

n Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard

Generalized Transmitter Block Diagram

10132002

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS101320

www.national.com

12 3 4 5 6 7...19

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与DS90C387A_06相关器件

型号	品牌	获取价格	描述	数据表
DS90C387AVJD	NSC	获取价格	Dual Pixel LVDS Display Interface / FPD-Link
DS90C387AVJD/NOPB	NSC	获取价格	IC 9 LINE DRIVER, PQFP100, TQFP-100, Line Driver or Receiver
DS90C387AVJD/NOPB	TI	获取价格	双像素 LVDS 显示接口/FPD 链接发送器 \| NEZ \| 100 \| -10 to
DS90C387MDC	TI	获取价格	IC,PARALLEL-TO-SERIAL CONVERTER,CMOS,DIE
DS90C387R	NSC	获取价格	85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA
DS90C387R	TI	获取价格	85MHz 双路 12 位双泵输入 LDI 发送器 VGA/UXGA
DS90C387RVJD	NSC	获取价格	85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA
DS90C387RVJD/NOPB	TI	获取价格	85MHz 双路 12 位双泵输入 LDI 发送器 VGA/UXGA \| NEZ \| 10
DS90C387RVJDX	NSC	获取价格	暂无描述
DS90C387RVJDX/NOPB	TI	获取价格	85MHz 双路 12 位双泵输入 LDI 发送器 VGA/UXGA \| NEZ \| 10

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