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DS90C387VJDX

更新时间： 2024-09-09 13:07:27

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
26页	520K
描述
IC 9 LINE DRIVER, PQFP100, TQFP-100, Line Driver or Receiver

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技术参数
数据手册
替代型号

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DS90C387VJDX 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	TQFP-100	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.12	Is Samacsys：	N
差分输出：	YES	驱动器位数：	9
输入特性：	STANDARD	接口集成电路类型：	LINE DRIVER
接口标准：	EIA-644; TIA-644	JESD-30 代码：	S-PQFP-G100
JESD-609代码：	e0	长度：	14 mm
湿度敏感等级：	3	功能数量：	9
端子数量：	100	最高工作温度：	70 °C
最低工作温度：	-10 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TFQFP	封装等效代码：	TQFP100,.63SQ
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	最大接收延迟：
座面最大高度：	1.2 mm	子类别：	Line Driver or Receivers
最大压摆率：	210 mA	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	14 mm	Base Number Matches：	1

DS90C387VJDX 数据手册

May 2004

DS90C387/DS90CF388

Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA

while maximizing bit times, and keeping clock rates low to

reduce EMI and shielding requirements. For more details,

please refer to the “Applications Information” section of this

datasheet.

General Description

The DS90C387/DS90CF388 transmitter/receiver pair is de-

signed to support dual pixel data transmission between Host

and Flat Panel Display up to QXGA resolutions. The trans-

mitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL

data into 8 LVDS (Low Voltage Differential Signalling) data

streams. Control signals (VSYNC, HSYNC, DE and two

user-defined signals) are sent during blanking intervals. At a

maximum dual pixel rate of 112MHz, LVDS data line speed is

672Mbps, providing a total throughput of 5.38Gbps (672

Megabytes per second). Two other modes are also sup-

ported. 24-bit color data (single pixel) can be clocked into the

transmitter at a maximum rate of 170MHz. In this mode, the

transmitter provides single-to-dual pixel conversion, and the

output LVDS clock rate is 85MHz maximum. The third mode

provides inter-operability with FPD-Link devices.

Features

n Complies with OpenLDI specification for digital display

interfaces

n 32.5 to 112/170MHz clock support for DS90C387, 40 to

112MHz clock support for DS90CF388

n Supports SVGA through QXGA panel resolutions

n Drives long, low cost cables

n Up to 5.38Gbps bandwidth

n Pre-emphasis reduces cable loading effects

n DC Balance data transmission provided by transmitter

reduces ISI distortion

The LDI chipset is improved over prior generations of FPD-

Link devices and offers higher bandwidth support and longer

cable drive with three areas of enhancement. To increase

bandwidth, the maximum pixel clock rate is increased to 112

(170) MHz and 8 serialized LVDS outputs are provided.

n Cable Deskew of +/−1 LVDS data bit time (up to 80

MHz Clock Rate) of pair-to-pair skew at receiver inputs;

intra-pair skew tolerance of 300ps

n Dual pixel architecture supports interface to GUI and

timing controller; optional single pixel transmitter inputs

support single pixel GUI interface

Cable drive is enhanced with

a user selectable pre-

emphasis feature that provides additional output current dur-

ing transitions to counteract cable loading effects. DC bal-

ancing on a cycle-to-cycle basis, is also provided to reduce

ISI (Inter-Symbol Interference). With pre-emphasis and DC

balancing, a low distortion eye-pattern is provided at the

receiver end of the cable. A cable deskew capability has

been added to deskew long cables of pair-to-pair skew of up

to +/−1 LVDS data bit time (up to 80 MHz Clock Rate). These

three enhancements allow cables 5+ meters in length to be

driven. This chipset is an ideal means to solve EMI and cable

size problems for high-resolution flat panel applications. It

provides a reliable interface based on LVDS technology that

delivers the bandwidth needed for high-resolution panels

n Transmitter rejects cycle-to-cycle jitter

n 5V tolerant on data and control input pins

n Programmable transmitter data and control strobe select

(rising or falling edge strobe)

n Backward compatible configuration select with FPD-Link

n Optional second LVDS clock for backward compatibility

w/ FPD-Link

n Support for two additional user-defined control signals in

DC Balanced mode

n Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS100073

www.national.com

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DS90C387VJDX 替代型号

型号	品牌	替代类型	描述	数据表
DS90C387AVJD/NOPB	NSC	功能相似	IC 9 LINE DRIVER, PQFP100, TQFP-100, Line Driver or Receiver

与DS90C387VJDX相关器件

型号	品牌	获取价格	描述	数据表
DS90C387VJDX/NOPB	TI	获取价格	+3.3V 双像素 LVDS 显示接口 (LDI)-SVGA/QXGA 发送器 \| NEZ
DS90C401	NSC	获取价格	Dual Low Voltage Differential Signaling (LVDS) Driver
DS90C401	TI	获取价格	双路低电压差动信号驱动器
DS90C401M	NSC	获取价格	Dual Low Voltage Differential Signaling (LVDS) Driver
DS90C401M	TI	获取价格	DS90C401 Dual Low Voltage Differential Signaling (LVDS) Driver
DS90C401M/NOPB	TI	获取价格	DS90C401 Dual Low Voltage Differential Signaling (LVDS) Driver
DS90C401MDC	NSC	获取价格	IC DUAL LINE DRIVER, UUC8, DIE, Line Driver or Receiver
DS90C401MX	TI	获取价格	DS90C401 Dual Low Voltage Differential Signaling (LVDS) Driver
DS90C401MX/NOPB	TI	获取价格	DS90C401 Dual Low Voltage Differential Signaling (LVDS) Driver
DS90C402	NSC	获取价格	Dual Low Voltage Differential Signaling (LVDS) Receiver

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