Datasheet > DS90C387

DS90C387

更新时间： 2023-09-03 20:32:52

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
34页	1236K
描述
+3.3V 双像素 LVDS 显示接口 (LDI)-SVGA/QXGA 发送器

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DS90C387 数据手册

DS90C387, DS90CF388

www.ti.com

SNLS012H –MAY 2000–REVISED APRIL 2013

DS90C387, DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA

Check for Samples: DS90C387, DS90CF388

FEATURES

DESCRIPTION

The DS90C387/DS90CF388 transmitter/receiver pair

•

Complies with OpenLDI Specification for

Digital Display Interfaces

is designed to support dual pixel data transmission

between Host and Flat Panel Display up to QXGA

resolutions. The transmitter converts 48 bits (Dual

Pixel 24-bit color) of CMOS/TTL data into 8 LVDS

(Low Voltage Differential Signalling) data streams.

Control signals (VSYNC, HSYNC, DE and two user-

defined signals) are sent during blanking intervals. At

a maximum dual pixel rate of 112MHz, LVDS data

line speed is 672Mbps, providing a total throughput of

5.38Gbps (672 Megabytes per second). Two other

modes are also supported. 24-bit color data (single

pixel) can be clocked into the transmitter at a

maximum rate of 170MHz. In this mode, the

transmitter provides single-to-dual pixel conversion,

and the output LVDS clock rate is 85MHz maximum.

The third mode provides inter-operability with FPD-

Link devices.

•

32.5 to 112/170MHz Clock Support for

DS90C387, 40 to 112MHz Clock Support for

DS90CF388

Supports SVGA through QXGA Panel

Resolutions

•

Drives Long, Low Cost Cables

Up to 5.38Gbps Bandwidth

Pre-Emphasis Reduces Cable Loading Effects

DC Balance Data Transmission Provided by

Transmitter Reduces ISI Distortion

•

Cable Deskew of +/−1 LVDS Data Bit Time (up

to 80 MHz Clock Rate) of Pair-to-Pair Skew at

Receiver Inputs; Intra-Pair Skew Tolerance of

300ps

The LDI chipset is improved over prior generations of

FPD-Link devices and offers higher bandwidth

support and longer cable drive with three areas of

enhancement. To increase bandwidth, the maximum

pixel clock rate is increased to 112 (170) MHz and 8

serialized LVDS outputs are provided. Cable drive is

•

Dual Pixel Architecture Supports Interface to

GUI and Timing Controller; Optional Single

Pixel Transmitter Inputs Support Single Pixel

GUI Interface

•

Transmitter Rejects Cycle-to-Cycle Jitter

5V Tolerant on Data and Control Input Pins

enhanced with

a user selectable pre-emphasis

feature that provides additional output current during

transitions to counteract cable loading effects. DC

balancing on a cycle-to-cycle basis, is also provided

to reduce ISI (Inter-Symbol Interference). With pre-

emphasis and DC balancing, a low distortion eye-

pattern is provided at the receiver end of the cable. A

cable deskew capability has been added to deskew

long cables of pair-to-pair skew of up to +/−1 LVDS

data bit time (up to 80 MHz Clock Rate). These three

enhancements allow cables 5+ meters in length to be

driven. This chipset is an ideal means to solve EMI

and cable size problems for high-resolution flat panel

applications. It provides a reliable interface based on

LVDS technology that delivers the bandwidth needed

for high-resolution panels while maximizing bit times,

and keeping clock rates low to reduce EMI and

shielding requirements. For more details, please refer

to Applications Information.

Programmable Transmitter Data and Control

Strobe Select (Rising or Falling Edge Strobe)

•

Backward Compatible Configuration Select

with FPD-Link

Optional Second LVDS Clock for Backward

Compatibility w/ FPD-Link

Support for Two Additional User-Defined

Control Signals in DC Balanced Mode

Compatible with ANSI/TIA/EIA-644-1995 LVDS

Standard

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...34

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DS90C387 替代型号

型号	品牌	替代类型	描述	数据表
DS90C185	TI	功能相似	Low Power 1.8V FPD-Link (LVDS) Serializer
DS90C187	TI	功能相似	Low Power 1.8V Dual Pixel FPD-Link (LVDS) Serializer

与DS90C387相关器件

型号	品牌	获取价格	描述	数据表
DS90C387_06	NSC	获取价格	Dual Pixel LVDS Display Interface (LDI)=SVGA/QXGA
DS90C387A	NSC	获取价格	Dual Pixel LVDS Display Interface / FPD-Link
DS90C387A	TI	获取价格	双像素 LVDS 显示接口/FPD 链接发送器
DS90C387A_06	NSC	获取价格	Dual Pixel LVDS Display Interface/FPD-Link
DS90C387AVJD	NSC	获取价格	Dual Pixel LVDS Display Interface / FPD-Link
DS90C387AVJD/NOPB	NSC	获取价格	IC 9 LINE DRIVER, PQFP100, TQFP-100, Line Driver or Receiver
DS90C387AVJD/NOPB	TI	获取价格	双像素 LVDS 显示接口/FPD 链接发送器 \| NEZ \| 100 \| -10 to
DS90C387MDC	TI	获取价格	IC,PARALLEL-TO-SERIAL CONVERTER,CMOS,DIE
DS90C387R	NSC	获取价格	85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA
DS90C387R	TI	获取价格	85MHz 双路 12 位双泵输入 LDI 发送器 VGA/UXGA

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