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DS90C124-Q1 PDF预览

DS90C124-Q1

更新时间： 2023-09-03 20:27:57
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德州仪器 - TI 光电二极管
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41页 1802K
描述
5MHz 至 35MHz 直流平衡 24 位汽车类 FPD-Link II 解串器

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DS90C124-Q1 数据手册

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DS90C124, DS90C241  
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017  
DS90C241 and DS90C124 5-MHz to 35-MHz DC-Balanced 24-Bit  
FPD-Link II Serializer and Deserializer  
1 Features  
2 Applications  
1
•
5-MHz to 35-MHz Clock Embedded and DC-  
Balancing 24:1 and 1:24 Data Transmissions  
•
•
•
•
Automotive Central Information Displays  
Automotive Instrument Cluster Displays  
Automotive Heads-Up Displays  
•
User Defined Pre-Emphasis Driving Ability  
Through External Resistor on LVDS Outputs and  
Capable to Drive Up to 10-Meter Shielded  
Twisted-Pair Cable  
Remote Camera-Based Driver Assistance  
Systems  
•
•
User-Selectable Clock Edge for Parallel Data on  
Both Transmitter and Receiver  
3 Description  
The DS90C241 and DS90C124 chipset translates a  
24-bit parallel bus into a fully transparent data and  
control LVDS serial stream with embedded clock  
information. This single serial stream simplifies  
transferring a 24-bit bus over PCB traces or over  
cable by eliminating the skew problems between  
parallel data and clock paths. It saves system cost by  
narrowing data paths, which in turn reduces PCB  
layers, cable width, and connector size and pins.  
Internal DC Balancing Encode and Decode  
(Supports AC-Coupling Interface With No External  
Coding Required)  
•
•
Individual Power-Down Controls for Both  
Transmitter and Receiver  
Embedded Clock CDR (Clock and Data Recovery)  
on Receiver and No External Source of Reference  
Clock Required  
The DS90C241 and DS90C124 incorporate LVDS  
signaling on the high-speed I/O. LVDS provides a  
low-power and low-noise environment for reliably  
transferring data over a serial transmission path. By  
optimizing the serializer output edge rate for the  
operating frequency range, EMI is further reduced.  
•
•
•
•
•
•
All Codes RDL (Random Data Lock) to Support  
Live-Pluggable Applications  
LOCK Output Flag to Ensure Data Integrity at  
Receiver Side  
Balanced TSETUP and THOLD Between RCLK and  
RDATA on Receiver Side  
In addition, the device features pre-emphasis to boost  
signals over longer distances using lossy cables.  
Internal DC balanced encoding and decoding  
supports AC-coupled interconnects.  
PTO (Progressive Turnon) LVCMOS Outputs to  
Reduce EMI and Minimize SSO Effects  
All LVCMOS Inputs and Control Pins Have  
Internal Pulldown  
Device Information(1)  
On-Chip Filters for PLLs on Transmitter and  
Receiver  
PART NUMBER  
PACKAGE  
BODY SIZE (NOM)  
DS90C124  
DS90C241  
TQFP (48)  
7.00 mm x 7.00 mm  
•
•
•
•
•
Temperature Range: –40°C to 105°C  
Greater Than 8-kV HBM ESD Tolerant  
Meets AEC-Q100 Compliance  
Power Supply Range: 3.3 V ± 10%  
48-Pin TQFP Package  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
Block Diagram  
PRE  
DEN  
VODSEL  
REN  
D
OUT  
+
R
+
IN  
24  
24  
R
D
OUT  
IN  
R -  
IN  
D
OUT  
-
TRFB  
TCLK  
Timing  
and  
Control  
PLL  
PLL  
LOCK  
RCLK  
RRFB  
RPWDNB  
Timing  
and  
Clock  
Recovery  
TPWDNB  
Control  
SERIALIZER œ DS90C241  
DESERIALIZER œ DS90C124  
Copyright © 2017, Texas Instruments Incorporated  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 
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DS90C124-Q1 替代型号

型号 品牌 替代类型 描述 数据表
DS90UR241 TI

功能相似

 5MHz 至 43MHz 直流平衡 24 位 FPD-Link II 串行器
DS90UR124 TI

功能相似

 5MHz 至 43MHz 直流平衡 24 位 FPD-Link II 解串器
DS90C124 TI

功能相似

 5MHz 至 35MHz 直流平衡 24 位 FPD-Link II 解串器

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DS90C124QVSX NSC

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DS90C185 TI

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DS90C185SQ/NOPB TI

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 		低功耗 FPD 链接 (LVDS) 串行器 | NJV | 48 | -10 to 70
DS90C185SQE/NOPB TI

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 		低功耗 FPD 链接 (LVDS) 串行器 | NJV | 48 | -10 to 70
DS90C185SQE-NOPB TI

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 		Low Power 1.8V FPD-Link (LVDS) Serializer
DS90C185SQ-NOPB TI

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 		Low Power 1.8V FPD-Link (LVDS) Serializer
DS90C185SQX/NOPB TI

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 		低功耗 FPD 链接 (LVDS) 串行器 | NJV | 48 | -10 to 70

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