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DS90UR124 PDF预览

DS90UR124

更新时间: 2024-09-24 11:13:27
品牌 Logo 应用领域
德州仪器 - TI 光电二极管
页数 文件大小 规格书
43页 1134K
描述
5MHz 至 43MHz 直流平衡 24 位 FPD-Link II 解串器

DS90UR124 数据手册

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DS90UR124-Q1, DS90UR241-Q1  
SNLS231O SEPTEMBER 2006REVISED APRIL 2015  
DS90URxxx-Q1 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and  
Deserializer Chipset  
1 Features  
2 Applications  
1
Supports Displays With 18-Bit Color Depth  
5-MHz to 43-MHz Pixel Clock  
Automotive Central Information Displays  
Automotive Instrument Cluster Displays  
Automotive Heads-Up Displays  
Automotive-Grade Product AEC-Q100 Grade 2  
Qualified  
Remote Camera-Based Driver Assistance  
Systems  
24:1 Interface Compression  
Embedded Clock With DC Balancing Supports  
AC-Coupled Data Transmission  
3 Description  
The DS90URxxx-Q1 chipset translates  
a 24-bit  
Capable to Drive up to 10 Meters Shielded  
Twisted-Pair Cable  
parallel bus into a fully transparent data/control FPD-  
Link II LVDS serial stream with embedded clock  
information. This chipset is ideally suited for driving  
graphical data to displays requiring 18-bit color depth:  
RGB666 + HS, VS, DE + three additional general-  
purpose data channels. This single serial stream  
simplifies transferring a 24-bit bus over PCB traces  
and cable by eliminating the skew problems between  
parallel data and clock paths. The device saves  
system cost by narrowing data paths that in turn  
reduce PCB layers, cable width, and connector size  
and pins.  
No Reference Clock Required (Deserializer)  
Meets ISO 10605 ESD – Greater than 8 kV HBM  
ESD Structure  
Hot Plug Support  
EMI Reduction – Serializer Accepts Spread  
Spectrum Input; Data Randomization and  
Shuffling on Serial Link; Deserializer Provides  
Adjustable PTO (Progressive Turnon) LVCMOS  
Outputs  
@Speed BIST (Built-In Self-Test) to Validate  
LVDS Transmission Path  
The DS90URxxx-Q1 incorporates FPD-Link II LVDS  
signaling on the high-speed I/O. FPD-Link II LVDS  
provides a low-power and low-noise environment for  
reliably transferring data over a serial transmission  
path. By optimizing the Serializer output edge rate for  
the operating frequency range, EMI is further  
reduced.  
Individual Power-Down Controls for Both  
Transmitter and Receiver  
Power Supply Range 3.3 V ±10%  
48-Pin TQFP Package for Transmitter and 64-Pin  
TQFP Package for Receiver  
Device Information(1)  
Temperature Range: –40°C to 105°C  
PART NUMBER  
DS90UR124-Q1  
DS90UR241-Q1  
PACKAGE  
TQFP (64)  
TQFP (48)  
BODY SIZE (NOM)  
10.00 mm × 10.00 mm  
7.00 mm × 7.00 mm  
Backward-Compatible Mode With  
DS90C241/DS90C124  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
Applications Diagram  
Block Diagram  
Display  
Host  
VODSEL  
PRE  
(Infotainment, Instrument Cluster, CID)  
(Graphics/Video Processor, ECU)  
DEN  
RAOFF  
REN  
DE  
DE  
FPD-Link II  
1 Pair  
RGB Data  
GB Data  
R
Video  
Source  
D
+
R
R
+
IN  
OUT  
LCD  
DS90UR241  
Serializer  
DS90UR124  
Deserialize  
Clock  
Clock  
24  
r
24  
R
OUT  
D
IN  
(LVDS)  
HSYNC  
VSYNC  
SYNC  
H
-
D
-
IN  
OUT  
TRFB  
TCLK  
VSYNC  
(LVCMOS)  
(LVCMOS)  
Timing  
and  
PLL  
RAOFF  
PLL  
LOCK  
RRFB  
RPWDNB  
BISTEN  
BISTM  
SLEW  
PTOSEL  
Control  
Timing  
and  
Clock  
Recovery  
TPWDNB  
RCLK  
PASS  
Control  
SERIALIZER ± DS90UR241  
DESERIALIZER ± DS90UR124  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 

DS90UR124 替代型号

型号 品牌 替代类型 描述 数据表
DS90UR241 TI

功能相似

5MHz 至 43MHz 直流平衡 24 位 FPD-Link II 串行器
DS90C124-Q1 TI

功能相似

5MHz 至 35MHz 直流平衡 24 位汽车类 FPD-Link II 解串器
DS90C124 TI

功能相似

5MHz 至 35MHz 直流平衡 24 位 FPD-Link II 解串器

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