Datasheet > 驱动程序和接口 > 线路驱动器或接收器> DS90C124QVS

DS90C124QVS

更新时间： 2024-01-29 15:53:05

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
26页	1040K
描述
5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

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替代型号

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DS90C124QVS 数据手册

January 8, 2008

DS90C241/DS90C124

5-35MHz DC-Balanced 24-Bit LVDS Serializer and

Deserializer

General Description

The DS90C241/DS90C124 Chipset translates a 24-bit paral-

lel bus into a fully transparent data/control LVDS serial stream

with embedded clock information. This single serial stream

simplifies transferring a 24-bit bus over PCB traces and cable

by eliminating the skew problems between parallel data and

clock paths. It saves system cost by narrowing data paths that

in turn reduce PCB layers, cable width, and connector size

and pins.

User selectable clock edge for parallel data on both

Transmitter and Receiver

Internal DC Balancing encode/decode – Supports AC-

coupling interface with no external coding required

Individual power-down controls for both Transmitter and

Receiver

Embedded clock CDR (clock and data recovery) on

Receiver and no external source of reference clock

needed

All codes RDL (random data lock) to support live-

pluggable applications

■

The DS90C241/DS90C124 incorporates LVDS signaling on

the high-speed I/O. LVDS provides a low power and low noise

environment for reliably transferring data over a serial trans-

mission path. By optimizing the serializer output edge rate for

the operating frequency range EMI is further reduced.

LOCK output flag to ensure data integrity at Receiver side

■

Balanced T_SETUP/T_HOLDbetween RCLK and RDATA on

Receiver side

PTO (progressive turn-on) LVCMOS outputs to reduce

EMI and minimize SSO effects

All LVCMOS inputs and control pins have internal

pulldown

■

In addition the device features pre-emphasis to boost signals

over longer distances using lossy cables. Internal DC bal-

anced encoding/decoding is used to support AC-Coupled

interconnects.

On-chip filters for PLLs on Transmitter and Receiver

Temperature range –40°C to +105°C

Greater than 8 kV HBM ESD tolerant

Meets AEC-Q100 compliance

■

Features

5 MHz–35 MHz clock embedded and DC-Balancing 24:1

■

and 1:24 data transmissions

User defined Pre-Emphasis driving ability through external

resistor on LVDS outputs and capable to drive up to 10

meters shielded twisted-pair cable

Power supply range 3.3V ± 10%

48-pin TQFP package

■

Block Diagram

20171901

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

201719

www.national.com

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DS90C124QVS 替代型号

型号	品牌	替代类型	描述	数据表
DS90C124QVSX	NSC	功能相似	5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

与DS90C124QVS相关器件

型号	品牌	获取价格	描述	数据表
DS90C124QVS/NOPB	TI	获取价格	5MHz 至 35MHz 直流平衡 24 位汽车类 FPD-Link II 解串器 \| P
DS90C124QVSX	NSC	获取价格	5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS90C124QVSX/NOPB	TI	获取价格	5MHz 至 35MHz 直流平衡 24 位汽车类 FPD-Link II 解串器 \| P
DS90C185	TI	获取价格	Low Power 1.8V FPD-Link (LVDS) Serializer
DS90C185SQ/NOPB	TI	获取价格	低功耗 FPD 链接 (LVDS) 串行器 \| NJV \| 48 \| -10 to 70
DS90C185SQE/NOPB	TI	获取价格	低功耗 FPD 链接 (LVDS) 串行器 \| NJV \| 48 \| -10 to 70
DS90C185SQE-NOPB	TI	获取价格	Low Power 1.8V FPD-Link (LVDS) Serializer
DS90C185SQ-NOPB	TI	获取价格	Low Power 1.8V FPD-Link (LVDS) Serializer
DS90C185SQX/NOPB	TI	获取价格	低功耗 FPD 链接 (LVDS) 串行器 \| NJV \| 48 \| -10 to 70
DS90C185SQX-NOPB	TI	获取价格	Low Power 1.8V FPD-Link (LVDS) Serializer

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