Datasheet > DS17285S-5

DS17285S-5

更新时间： 2024-02-13 00:58:04

品牌	Logo	应用领域
达拉斯 - DALLAS		时钟
页数	文件大小	规格书
38页	408K
描述
3V/5V Real-Time Clock

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DS17285S-5 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SO-24	针数：	24
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	10 weeks
风险等级：	5.1	Is Samacsys：	N
最大时钟频率：	0.032 MHz	外部数据总线宽度：	8
信息访问方法：	PARALLEL, MUXED BUS	中断能力：	Y
JESD-30 代码：	R-PDSO-G24	JESD-609代码：	e3
长度：	17.9 mm	湿度敏感等级：	1
端子数量：	24	计时器数量：	1
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP24,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	2.68 mm	子类别：	Timer or RTC
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
最短时间：	SECONDS	处于峰值回流温度下的最长时间：	NOT SPECIFIED
易失性：	YES	宽度：	7.5 mm
uPs/uCs/外围集成电路类型：	TIMER, REAL TIME CLOCK	Base Number Matches：	1

DS17285S-5 数据手册

DS17285/DS17287

RTC ADDRESS MAP

The address map for the RTC registers of the DS17285/DS17287 is shown in Figure 2. The address map

consists of the 14 clock/calendar registers. Ten registers contain the time, calendar, and alarm data, and

4 bytes are used for control and status. All registers can be directly written or read except for the

following:

1) Registers C and D are read-only.

2) Bit 7 of Register A is read-only.

3) The high order bit of the second byte is read-only.

Figure 2. DS17285 REAL-TIME CLOCK ADDRESS MAP

TIME, CALENDAR, AND ALARM LOCATIONS

The time and calendar information is obtained by reading the appropriate register bytes shown in Table 1.

The time, calendar, and alarm are set or initialized by writing the appropriate register bytes. The contents

of the time, calendar, and alarm registers can be either binary or binary-coded decimal (BCD) format.

Table 1 shows the binary and BCD formats of the 10 time, calendar, and alarm locations that reside in

both bank 0 and in bank 1, plus the two extended registers that reside in bank 1 only (bank 0 and

bank 1 switching is explained later in this text).

Before writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written

to a logic 1 to prevent updates from occurring while access is being attempted. Also at this time, the data

format (binary or BCD) should be set by the data mode bit (DM) of Register B. All time, calendar, and

alarm registers must use the same data mode. The set bit in Register B should be cleared after the data

mode bit has been written to allow the real-time clock to update the time and calendar bytes.

Once initialized, the real time clock makes all updates in the selected mode. The data mode cannot be

changed without reinitializing the 10 data bytes. The 24/12 bit cannot be changed without reinitializing

the hour locations. When the 12-hour format is selected, the high order bit of the hours byte represents

PM when it is a logic 1. The time, calendar, and alarm bytes are always accessible because they are

double-buffered. Once per second the 10 bytes are advanced by 1 second and checked for an alarm

condition. If a read of the time and calendar data occurs during an update, a problem exists where

seconds, minutes, hours, etc., may not correlate. The probability of reading incorrect time and calendar

data is low. Several methods of avoiding any possible incorrect time and calendar reads are covered later

in this text.

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与DS17285S-5相关器件

型号	品牌	描述	获取价格	数据表
DS17285S-5/T&R	MAXIM	Real Time Clock, Volatile, 1 Timer(s), CMOS, PDSO24, 0.300 INCH, SOP-24	获取价格
DS17285S-5+	MAXIM	Real-Time Clocks	获取价格
DS17285S-5+T&R	MAXIM	Real Time Clock, Volatile, 1 Timer(s), CMOS, PDSO24, SO-24	获取价格
DS17285SN-	MAXIM	Real-Time Clocks	获取价格
DS17285SN3	MAXIM	Real-Time Clocks	获取价格
DS17285SN-3	DALLAS	3V/5V Real-Time Clock	获取价格

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