DP83241BV

更新时间： 2024-01-31 13:32:59

品牌	Logo	应用领域
美国国家半导体 - NSC		电信集成电路电信电路信息通信管理时钟
页数	文件大小	规格书
20页	251K
描述
CDD Device (FDDI Clock Distribution Device)

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技术参数
数据手册

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DP83241BV 技术参数

生命周期：	Obsolete	包装说明：	QCCJ,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	JESD-30 代码：	S-PQCC-J28
长度：	11.5062 mm	功能数量：	1
端子数量：	28	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	认证状态：	Not Qualified
座面最大高度：	4.57 mm	表面贴装：	YES
电信集成电路类型：	TELECOM CIRCUIT	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	11.5062 mm

DP83241BV 数据手册

3.0 Pin Descriptions (Continued)

Symbol

I/O

Description

No.

VCO RST

VCO Reset: TTL compatible input used to reset the internal VCO on system power up. This input

stops the VCO from oscillating when at a logic HI level thereby reinitializing each of the gates in

the ring oscillator.

TXC^a

TXC^b

Transmit Clock: 100K ECL compatible differential outputs for use at 125 MHz as the fiber

medium Transmit Clock (TXC) source for the PLAYER device.

TBC^a

TBC^b

27,

Transmit Byte Clock: 100K ECL compatible differential outputs for use at 12.5 MHz as a load

strobe or transmit byte clock by the PLAYER device to convert byte wide data to serial format for

fiber medium transmission. These outputs are positioned to transition on the falling edge of the

coherent with the TTL LBC1 output, but the phase transition occurs approximately 10 ns earlier.

TXC

clock output to provide the maximum setup and hold margin. They are also phase

LBC1 thru 5

LSC

25, 24,

Local Byte Clocks: TTL compatible local byte clock outputs which are phase locked to crystal

oscillator reference signals. These outputs have a 50% duty cycle waveform at 12.5 MHz. The

PHASE SEL input determines whether the five phase outputs are phase offset by 8 ns or 16 ns.

23, 22, 21

Local Symbol Clock: TTL compatible 25 MHz output for driving the BMAC device. This output’s

negative phase transition is aligned with the LBC1 output transitions and has a 40% HI and 60%

LOW duty cycle.

PHASE SEL

Phase Select: TTL compatible input used to select either a 8 ns or 16 ns phase offset between

the 5 local byte clocks. The LBC’s are phase offset 8 ns apart when PHASE SEL is at a logic LOW

level and 16 ns apart when at a logic HI level.

1...3 4 567 8 9...20

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