DP83241BV

更新时间： 2024-02-25 14:41:54

品牌	Logo	应用领域
美国国家半导体 - NSC		电信集成电路电信电路信息通信管理时钟
页数	文件大小	规格书
20页	251K
描述
CDD Device (FDDI Clock Distribution Device)

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技术参数
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DP83241BV 技术参数

生命周期：	Obsolete	包装说明：	QCCJ,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	JESD-30 代码：	S-PQCC-J28
长度：	11.5062 mm	功能数量：	1
端子数量：	28	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	认证状态：	Not Qualified
座面最大高度：	4.57 mm	表面贴装：	YES
电信集成电路类型：	TELECOM CIRCUIT	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	11.5062 mm

DP83241BV 数据手册

2.0 Functional Description

The CDD device clocks are all generated from and phase

aligned to either a 12.5 MHz crystal oscillator or a TTL input

reference source using digital phase locked loop tech-

niques. The architecture of the Clock Distribution Device en-

sures that the output clocks which are generated have fre-

quency tolerances identical to the 50 PPM crystal reference.

When the reference input signal is a backplane signal, the

matching of the phase comparator input path delays guar-

antees phase alignment within 3 ns.

mon reference signal. The VCO SEL input provides the op-

tion to use the internally provided VCO or an external LC

voltage controlled oscillator. Although the stability of the in-

ternal VCO should be adequate for most applications the

external VCO option provides the means of obtaining the

maximum possible oscillator Q. The PHASE SEL input pin

provides the option of selecting whether the five phase LBC

outputs are phase offset 36 degrees or 72 degrees (8 ns or

16 ns).

The phase locked loop generates the desired clocks as

shown in the device Block Diagram. One of the Local Byte

Clock (LBC) phases is connected to the FEEDBK IN input of

the phase comparator where its phase and frequency are

compared against that of the selected input reference sig-

nal. Any phase error between these signals results in a cor-

rection of the voltage into the Voltage Controlled Oscillator

(VCO) which is proportional to the amount of phase error.

The correction voltage tends to drive the frequency of the

VCO in the direction which, when divided down, minimizes

the LBC to reference signal phase difference. When the

phase transition of the LBC occurs before that of the refer-

ence input the VCO frequency is sensed as being too fast

and produces a negative going correction to the VCO input.

This in turn slows down the VCO’s frequency and delays the

subsequent LBC phase transitions.

The phase locked loop (PLL) elements, with the exception

of the loop filter which consist of two capacitors and a resis-

tor, are fully contained within the device. The internal VCO

associated with the PLL has been implemented totally with-

in the device and requires no external LC oscillator tank

coils, capacitors, or varactors. The external VCO option

does provide a means of using these conventional LC oscil-

lator techniques if desired.

Connection Diagram

28-Pin PLCC Package

The device’s differential 125 MHz ECL transmit clock and

differential 12.5 MHz ECL load strobe are used by the

PLAYER device to convert data from byte wide NRZ format

to serial NRZI format for fiber medium transmission. A

12.5 MHz TTL local byte clock is provided for use by the

PLAYER and the BMAC devices. Five phases of the local

byte clock are provided for use in large multi-board concen-

trator configurations to aid in cancelling out backplane de-

lays. A 25 MHz Local Symbol Clock (LSC) is provided which

is in phase with the local byte clocks and has a 40% HIGH

and 60% LOW duty cycle.

TL/F/10385–25

Order Number DP83241BV

See NS Package Number V28A

The device provides three user-selectable features. The

REF SEL input provides the option to lock the device’s out-

puts to a crystal oscillator or to an external TTL signal (REF

IN). The REF IN signal is particularly useful in concentrators

where multiple boards need to be phase locked to a com-

FIGURE 2-1. DP83241 Pinout

Block Diagram

TL/F/10385–3

FIGURE 2-2. DP83241 Block Diagram

1 2 345 6 7...20

中文翻译

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与DP83241BV相关器件

型号	品牌	获取价格	描述	数据表
DP83241BVX	TI	获取价格	SPECIALTY TELECOM CIRCUIT, PQCC28, PLASTIC, LCC-28
DP83241V	ETC	获取价格	Miscellaneous Clock Generator
DP83251	NSC	获取价格	PLAYER Device (FDDI Physical Layer Controller)
DP83251V	NSC	获取价格	PLAYER Device (FDDI Physical Layer Controller)
DP83255	NSC	获取价格	PLAYER Device (FDDI Physical Layer Controller)
DP83255AVF	NSC	获取价格	PLAYER Device (FDDI Physical Layer Controller)
DP83255VF	ETC	获取价格	Communications Controller
DP83256	NSC	获取价格	PLAYERa+⑩ Device (FDDI Physical Layer Control
DP83256VF	NSC	获取价格	PLAYERa+⑩ Device (FDDI Physical Layer Control
DP83256VF-AP	NSC	获取价格	PLAYERa+⑩ Device (FDDI Physical Layer Control

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