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DP83266VF-MPC PDF预览

DP83266VF-MPC

更新时间: 2024-01-20 04:48:28
品牌 Logo 应用领域
德州仪器 - TI 外围集成电路
页数 文件大小 规格书
152页 944K
描述
1 CHANNEL(S), FDDI CONTROLLER, PQFP16, PLASTIC, QFP-160

DP83266VF-MPC 技术参数

生命周期:Obsolete包装说明:QFP,
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.83地址总线宽度:32
边界扫描:YES外部数据总线宽度:32
JESD-30 代码:S-PQFP-G16长度:28 mm
低功率模式:YES串行 I/O 数:1
端子数量:16最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK认证状态:Not Qualified
座面最大高度:3.7 mm最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
宽度:28 mmuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, FDDI
Base Number Matches:1

DP83266VF-MPC 数据手册

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PRELIMINARY  
October 1994  
DP83266 MACSITM Device  
(FDDI Media Access Controller and System Interface)  
Y
On-chip address bit swapping capability  
General Description  
The DP83266 Media Access Controller and System Inter-  
Y
32-bit wide Address/Data path with byte parity  
Y
Programmable transfer burst sizes of 4 or 8  
face (MACSI) implements the ANSI X3T9.5 Standard Media  
32-bit words  
Access Control (MAC) protocol for operation in an FDDI  
token ring and provides a comprehensive System Interface.  
Y
Receive frame filtering services  
Y
Frame-per-Page mode controllable on each  
DMA channel  
The MACSI device transmits, receives, repeats, and strips  
tokens and frames. It produces and consumes optimized  
data structures for efficient data transfer. Full duplex archi-  
tecture with through parity allows diagnostic transmission  
and self testing for error isolation and point-to-point connec-  
tions.  
Y
Demultiplexed Addresses supported on ABus  
Y
New multicast address matching feature  
Y
ANSI X3T9.5 MAC standard defined ring  
service options  
Y
Y
Supports all FDDI Ring Scheduling Classes  
(Synchronous, Asynchronous, etc.)  
Supports Individual, Group, Short, Long and  
External Addressing  
The MACSI device includes the functionality of both the  
DP83261 BMACTM device and the DP83265 BSI-2TM device  
with additional enhancements for higher performance and  
reliability.  
Y
Y
Y
Y
Y
Y
Y
Generates Beacon, Claim, and Void frames  
Extensive ring and station statistics gathering  
Extensions for MAC level bridging  
Enhanced SBus compatibility  
Features  
Y
Over 9 kBytes of on-chip FIFO  
Y
5 DMA channels (2 Output and 3 Input)  
Y
Interfaces to DRAMs or directly to system bus  
Supports frame Header/Info splitting  
Programmable Big or Little Endian alignment  
12.5 MHz to 25 MHz operation  
Y
Full duplex operation with through parity  
Y
Supports JTAG boundary scan  
Y
Real-time Void stripping indicator for bridges  
Block Diagram  
TL/F/11705–1  
FIGURE 1-1. FDDI Chip Set Block Diagram  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
TM  
BMACTM, BSI-2TM, MACSITM and PLAYER  
are trademarks of National Semiconductor Corporation.  
a
C
1995 National Semiconductor Corporation  
TL/F/11705  
RRD-B30M105/Printed in U. S. A.  

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