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DM74S182N

更新时间： 2024-11-08 22:54:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 运算电路逻辑集成电路光电二极管
页数 文件大小 规格书
5页 57K
描述
Look-Ahead Carry Generator

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中文翻译

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DM74S182N 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP16,.3针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.3其他特性：WITH HIGHER ORDER LOOKAHEAD
系列：SJESD-30 代码：R-PDIP-T16
JESD-609代码：e0长度：19.305 mm
逻辑集成电路类型：LOOK-AHEAD CARRY GENERATOR位数：4
功能数量：1端子数量：16
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
传播延迟（tpd）：11 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Arithmetic Circuits
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：TTL温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
Base Number Matches：1

DM74S182N 数据手册

 浏览型号DM74S182N的Datasheet PDF文件第2页浏览型号DM74S182N的Datasheet PDF文件第3页浏览型号DM74S182N的Datasheet PDF文件第4页浏览型号DM74S182N的Datasheet PDF文件第5页 
August 1986  
Revised March 2000  
DM74S182  
Look-Ahead Carry Generator  
puts, generate, and propagate) of the look-ahead genera-  
tors are implemented in the compatible forms for direct  
connection to the ALU. Reinterpretations of carry functions,  
as explained on the 181 data sheet are also applicable to  
and compatible with the look-ahead generator. Positive  
logic equations for the DM74S182 are:  
General Description  
These circuits are high-speed, look-ahead carry genera-  
tors, capable of anticipating a carry across four binary  
adders or groups of adders. They are cascadable to per-  
form full look-ahead across n-bit adders. Carry, generate-  
carry, and propagate-carry functions are provided as  
shown in the pin designation table.  
C
C
C
n + x = G0 + P0 Cn  
n + y = G1 + P1 G0 + P1 P0 Cn  
n + z = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 Cn  
When used in conjunction with the 181 arithmetic logic unit,  
these generators provide high-speed carry look-ahead  
capability for any word length. Each DM74S182 generates  
the look-ahead (anticipated carry) across a group of four  
ALU’s and, in addition, other carry look-ahead circuits may  
be employed to anticipate carry across sections of four  
look-ahead packages up to n-bits. The method of cascad-  
ing circuits to perform multi-level look-ahead is illustrated  
under typical application data.  
G = G3 (P3 + G2) (P3 + P2 + G1)  
(P3 + P2 + P1 + G0)  
P = P3 P2 P1 P0  
Features  
■ Typical propagation delay time 7 ns  
Carry input and output of the ALU’s are in their true form,  
and the carry propagate (P) and carry generate (G) are in  
negated form; therefore, the carry functions (inputs, out-  
■ Typical power dissipation 260 mW  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74S182N  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Connection Diagram  
Pin Designations  
Designation  
Pin Nos.  
Function  
Active LOW  
G0, G1, G2, G3  
3, 1, 14, 5  
Carry Generate Inputs  
Active LOW  
P0, P1, P2, P3  
4, 2, 15, 6  
Carry Propagate Inputs  
Carry Input  
Cn  
13  
Cn + x, Cn + y  
,
12, 11, 9  
Carry Outputs  
Cn + z  
G
10  
7
Active LOW  
Carry Generate Output  
Active LOW  
P
Carry Propagate Output  
Supply Voltage  
Ground  
VCC  
16  
8
GND  
© 2000 Fairchild Semiconductor Corporation  
DS006474  
www.fairchildsemi.com  
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