DM74LS85ASJ

更新时间： 2024-09-12 23:00:43

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器
页数	文件大小	规格书
6页	70K
描述
Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs

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DM74LS85ASJ 数据手册

August 1986

Revised March 2000

DM74LS74A

Dual Positive-Edge-Triggered D Flip-Flops with

Preset, Clear and Complementary Outputs

General Description

This device contains two independent positive-edge-trig-

gered D flip-flops with complementary outputs. The infor-

mation on the D input is accepted by the flip-flops on the

positive going edge of the clock pulse. The triggering

occurs at a voltage level and is not directly related to the

transition time of the rising edge of the clock. The data on

the D input may be changed while the clock is LOW or

HIGH without affecting the outputs as long as the data

setup and hold times are not violated. A low logic level on

the preset or clear inputs will set or reset the outputs

regardless of the logic levels of the other inputs.

Ordering Code:

Order Number Package Number

Package Description

DM74LS74AM

DM74LS85ASJ

DM74LS74AN

M14A

M14D

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

Outputs

CLR

CLK

H (Note 1) H (Note 1)

↑

Q₀

H = HIGH Logic Level

X = Either LOW or HIGH Logic Level

L = LOW Logic Level

↑ = Positive-going Transition

= The output logic level of Q before the indicated input conditions were

established.

Note 1: This configuration is nonstable; that is, it will not persist when either

the preset and/or clear inputs return to their inactive (HIGH) level.

DS006373

www.fairchildsemi.com

12 3 4 5 6

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