DM74LS491

更新时间： 2024-11-27 23:00:43

品牌	Logo	应用领域
美国国家半导体 - NSC		计数器
页数	文件大小	规格书
4页	130K
描述
10-Bit Counter

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数据手册

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DM74LS491 数据手册

July 1989

DM54LS491/74LS491 10-Bit Counter

General Description

Features/Benefits

CRT vertical and horizontal timing generation

The ten-bit counter can count up, count down, set, and load

2 LSB’s, 2 MSB’s and 6 middle bits high or low as a group.

All operations are synchronous with the clock. SET over-

rides LOAD, COUNT and HOLD. LOAD overrides COUNT.

Bus-structured pinout

24-pin SKINNYDIP saves space

TRI-STATE outputs drive bus lines

Low current PNP inputs reduce loading

COUNT is conditional on C , otherwise it holds.

All outputs are enabled when OE is low, otherwise HIGH-Z.

The 24 mA I outputs are suitable for driving RAM/PROM

address lines in video graphics systems.

Connection Diagram

Standard Test Load

Top View

TL/L/8332–2

TL/L/8332–1

Order Number DM54LS491J,

DM74LS491J or DM74LS491N

See NS Package Number J24F or N24C

Function Table

OE CK SET LD CNT C UP D9-D0 Q9-Q0 Operation

Hi-Z

Set all HIGH

LOAD D

HOLD

Q plus 1 Count UP

Q minus 1 Count DN

TRI-STATEÉ is a registered trademark of National Semiconductor Corp.

1995 National Semiconductor Corporation

TL/L/8332

RRD-B30M115/Printed in U. S. A.

12 3 4

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与DM74LS491相关器件

型号	品牌	获取价格	描述	数据表
DM74LS491AJ	TI	获取价格	LS SERIES, SYN POSITIVE EDGE TRIGGERED 10-BIT BIDIRECTIONAL BINARY COUNTER, CDIP24, SKINNY
DM74LS491AN	TI	获取价格	LS SERIES, SYN POSITIVE EDGE TRIGGERED 10-BIT BIDIRECTIONAL BINARY COUNTER, PDIP24, SKINNY
DM74LS491AV	ETC	获取价格	Synchronous Up/Down Counter
DM74LS491J	NSC	获取价格	10-Bit Counter
DM74LS491J	TI	获取价格	LS SERIES, SYN POSITIVE EDGE TRIGGERED 10-BIT BIDIRECTIONAL BINARY COUNTER, CDIP24, SKINNY
DM74LS491J/A+	ETC	获取价格	Synchronous Up/Down Counter
DM74LS491J/B+	ETC	获取价格	Synchronous Up/Down Counter
DM74LS491N	NSC	获取价格	10-Bit Counter
DM74LS491N	TI	获取价格	LS SERIES, SYN POSITIVE EDGE TRIGGERED 10-BIT BIDIRECTIONAL BINARY COUNTER, PDIP24, SKINNY
DM74LS491N/A+	ETC	获取价格	Synchronous Up/Down Counter