April 1998
DM74LS469
8-Bit Up/Down Counter
The output register (Q7–Q0) is enabled when OE is LOW,
and disabled (HI-Z) when OE is HIGH. The output drivers will
sink the 24 mA required for many bus-interface standards.
Two or more ’LS469 octal up/down counters may be cas-
caded to provide larger counters.
General Description
The ’LS469 is an 8-bit synchronous up/down counter with
parallel load and hold capability. Three function-select inputs
(LD, UD, CBI) provide one of four operations which occur
synchronously on the rising edge of the clock (CK).
The LOAD operation loads the inputs (D7–D0) into the output
register (Q7–Q0). The HOLD operation holds the previous
value regardless of clock transitions. The INCREMENT op-
eration adds one to the output register when the carry-in in-
Features/Benefits
n 8-bit up/down counter for microprogram-counter, DMA
controller and general-purpose counting applications
n 8 bits matches byte boundaries
=
put is TRUE (CBI LOW), otherwise the operation is a
n Bus-structured pinout
=
HOLD. The carry-out (CBO) is TRUE (CBO LOW) when
n 24-pin SKINNYDIP saves space
the output register (Q7–Q0) is all HIGHs, otherwise FALSE
=
(CBO HIGH). The DECREMENT operation subtracts one
n 3-STATE outputs drive bus lines
from the output register when the borrow-in input is TRUE
n Low current PNP inputs reduce loading
n Expandable in 8-bit increments
=
(CBI LOW), otherwise the operation is
a HOLD. The
=
borrow-out (CBO) is TRUE (CBO LOW) when the output
register (Q7–Q0) is all LOWs, otherwise FALSE (CBO
=
HIGH).
Connection Diagram
Standard Test Load
Top View
DS008333-3
DS008333-1
Order Number DM54LS469J,
DM74LS469J or DM74LS469N
See Package Number J24F or N24C
© 1998 Fairchild Semiconductor Corporation
DS008333
www.fairchildsemi.com