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DM74LS469N PDF预览

DM74LS469N

更新时间: 2024-02-16 16:34:12
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美国国家半导体 - NSC 计数器
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4页 125K
描述
DM54LS469/DM74LS469 8-Bit Up/Down Counter

DM74LS469N 数据手册

 浏览型号DM74LS469N的Datasheet PDF文件第2页浏览型号DM74LS469N的Datasheet PDF文件第3页浏览型号DM74LS469N的Datasheet PDF文件第4页 
July 1989  
DM54LS469/DM74LS469 8-Bit Up/Down Counter  
General Description  
The ‘LS469 is an 8-bit synchronous up/down counter with  
parallel load and hold capability. Three function-select in-  
puts (LD, UD, CBI) provide one of four operations which  
occur synchronously on the rising edge of the clock (CK).  
The output register (Q Q ) is enabled when OE is LOW,  
7 0  
and disabled (HI-Z) when OE is HIGH. The output drivers  
will sink the 24 mA required for many bus-interface stan-  
dards. Two or more ‘LS469 octal up/down counters may be  
cascaded to provide larger counters.  
The LOAD operation loads the inputs (D D ) into the out-  
7
0
put register (Q Q ). The HOLD operation holds the previ-  
7
0
Features/Benefits  
Y
ous value regardless of clock transitions. The INCREMENT  
operation adds one to the output register when the carry-in  
8-bit up/down counter for microprogram-counter, DMA  
controller and general-purpose counting applications  
e
input is TRUE (CBI LOW), otherwise the operation is a  
HOLD. The carry-out (CBO) is TRUE (CBO LOW) when  
e
Y
8 bits matches byte boundaries  
the output register (Q Q ) is all HIGHs, otherwise FALSE  
0
Y
7
Bus-structured pinout  
e
(CBO HIGH). The DECREMENT operation subtracts one  
from the output register when the borrow-in input is TRUE  
Y
24-pin SKINNYDIP saves space  
Y
TRI-STATE outputs drive bus lines  
É
Low current PNP inputs reduce loading  
e
(CBI LOW), otherwise the operation is a HOLD. The bor-  
row-out (CBO) is TRUE (CBO LOW) when the output reg-  
Y
e
Y
Expandable in 8-bit increments  
e
ister (Q Q ) is all LOWs, otherwise FALSE (CBO HIGH).  
7
0
Connection Diagram  
Standard Test Load  
Top View  
TL/L/8333–3  
TL/L/8333–1  
Order Number DM54LS469J,  
DM74LS469J or DM74LS469N  
See NS Package Number J24F or N24C  
Function Table  
OE CK LD UD CBI D7D0 Q7Q0  
Operation  
H
L
L
L
L
L
X
X
L
X
X
L
X
X
H
L
X
D
X
X
X
X
Z
D
Q
HI-Z  
LOAD  
HOLD  
u
u
u
u
u
H
H
H
H
L
Q plus 1 INCREMENT  
HOLD  
Q minus 1 DECREMENT  
H
H
H
L
Q
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.  
C
1995 National Semiconductor Corporation  
TL/L/8333  
RRD-B30M115/Printed in U. S. A.  

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