5秒后页面跳转
DM74LS469J PDF预览

DM74LS469J

更新时间: 2024-09-20 23:00:43
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器触发器逻辑集成电路输出元件输入元件
页数 文件大小 规格书
4页 125K
描述
DM54LS469/DM74LS469 8-Bit Up/Down Counter

DM74LS469J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP24,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
其他特性:TCO OUTPUT; COUNT ENABLE INPUT计数方向:BIDIRECTIONAL
系列:LSJESD-30 代码:R-GDIP-T24
JESD-609代码:e0负载电容(CL):50 pF
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:12500000 Hz最大I(ol):0.024 A
工作模式:SYNCHRONOUS位数:8
功能数量:1端子数量:24
最高工作温度:75 °C最低工作温度:
输出特性:3-STATE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP24,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):180 mA传播延迟(tpd):30 ns
认证状态:Not Qualified座面最大高度:5.715 mm
子类别:Counters最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL EXTENDED端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:12.5 MHzBase Number Matches:1

DM74LS469J 数据手册

 浏览型号DM74LS469J的Datasheet PDF文件第2页浏览型号DM74LS469J的Datasheet PDF文件第3页浏览型号DM74LS469J的Datasheet PDF文件第4页 
July 1989  
DM54LS469/DM74LS469 8-Bit Up/Down Counter  
General Description  
The ‘LS469 is an 8-bit synchronous up/down counter with  
parallel load and hold capability. Three function-select in-  
puts (LD, UD, CBI) provide one of four operations which  
occur synchronously on the rising edge of the clock (CK).  
The output register (Q Q ) is enabled when OE is LOW,  
7 0  
and disabled (HI-Z) when OE is HIGH. The output drivers  
will sink the 24 mA required for many bus-interface stan-  
dards. Two or more ‘LS469 octal up/down counters may be  
cascaded to provide larger counters.  
The LOAD operation loads the inputs (D D ) into the out-  
7
0
put register (Q Q ). The HOLD operation holds the previ-  
7
0
Features/Benefits  
Y
ous value regardless of clock transitions. The INCREMENT  
operation adds one to the output register when the carry-in  
8-bit up/down counter for microprogram-counter, DMA  
controller and general-purpose counting applications  
e
input is TRUE (CBI LOW), otherwise the operation is a  
HOLD. The carry-out (CBO) is TRUE (CBO LOW) when  
e
Y
8 bits matches byte boundaries  
the output register (Q Q ) is all HIGHs, otherwise FALSE  
0
Y
7
Bus-structured pinout  
e
(CBO HIGH). The DECREMENT operation subtracts one  
from the output register when the borrow-in input is TRUE  
Y
24-pin SKINNYDIP saves space  
Y
TRI-STATE outputs drive bus lines  
É
Low current PNP inputs reduce loading  
e
(CBI LOW), otherwise the operation is a HOLD. The bor-  
row-out (CBO) is TRUE (CBO LOW) when the output reg-  
Y
e
Y
Expandable in 8-bit increments  
e
ister (Q Q ) is all LOWs, otherwise FALSE (CBO HIGH).  
7
0
Connection Diagram  
Standard Test Load  
Top View  
TL/L/8333–3  
TL/L/8333–1  
Order Number DM54LS469J,  
DM74LS469J or DM74LS469N  
See NS Package Number J24F or N24C  
Function Table  
OE CK LD UD CBI D7D0 Q7Q0  
Operation  
H
L
L
L
L
L
X
X
L
X
X
L
X
X
H
L
X
D
X
X
X
X
Z
D
Q
HI-Z  
LOAD  
HOLD  
u
u
u
u
u
H
H
H
H
L
Q plus 1 INCREMENT  
HOLD  
Q minus 1 DECREMENT  
H
H
H
L
Q
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.  
C
1995 National Semiconductor Corporation  
TL/L/8333  
RRD-B30M115/Printed in U. S. A.  

与DM74LS469J相关器件

型号 品牌 获取价格 描述 数据表
DM74LS469J/A+ ETC

获取价格

Synchronous Up/Down Counter
DM74LS469J/B+ ETC

获取价格

Synchronous Up/Down Counter
DM74LS469N NSC

获取价格

DM54LS469/DM74LS469 8-Bit Up/Down Counter
DM74LS469N/A+ ETC

获取价格

Synchronous Up/Down Counter
DM74LS469N/B+ ETC

获取价格

Synchronous Up/Down Counter
DM74LS47 FAIRCHILD

获取价格

BCD to 7-Segment Decoder/Driver with Open-Collector Outputs
DM74LS47 NSC

获取价格

BCD TO 7-SEGMENT DECODER/DRIVER
DM74LS47_07 FAIRCHILD

获取价格

BCD to 7-Segment Decoder/Driver with Open-Collector Outputs
DM74LS471J NSC

获取价格

(256 X 8) 2048-BIT TTL PROM
DM74LS471J/A+ ETC

获取价格

x8 PROM