DM74LS299WM

更新时间： 2024-01-09 23:28:19

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		存储
页数	文件大小	规格书
6页	68K
描述
8-Input Universal Shift/Storage Register with

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数据手册

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DM74LS299WM 数据手册

October 1988

Revised March 2000

DM74LS299

8-Input Universal Shift/Storage Register with

Common Parallel I/O Pins

General Description

Features

■ Common I/O for reduced pin count

The DM74LS299 is an 8-bit universal shift/storage register

with 3-STATE outputs. Four modes of operation are possi-

ble: hold (store), shift left, shift right and load data. The par-

allel load inputs and flip-flop outputs are multiplexed to

reduce the total number of package pins. Separate outputs

are provided for flip-flops Q0 and Q7 to allow easy cascad-

ing. A separate active LOW Master Reset is used to reset

the register.

■ Four operation modes: shift left, shift right, load and

store

■ Separate shift right serial input and shift left serial input

for easy cascading

■ 3-STATE outputs for bus oriented applications

Ordering Code:

Order Number Package Number

Package Description

DM74LS299WM

DM74LS299N

M20B

N20A

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram

= Pin 20

GND = Pin 10

Pin Descriptions

Names

Description

Clock Pulse Input (Active Rising Edge)

Serial Data Input for Right Shift

Serial Data Input for Left Shift

D_S0

D_S7

S0, S1

Mode Select Inputs

Asynchronous Master Reset Input (Active LOW)

OE1, OE2 3-STATE Output Enable Inputs (Active LOW)

I/O0–I/O7 Parallel Data Inputs or 3-STATE Parallel Outputs

Q0–Q7

Serial Outputs

DS009827

www.fairchildsemi.com

12 3 4 5 6

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