Datasheet > 逻辑 > 计数器> DM74LS163AM

DM74LS163AM

更新时间： 2024-11-26 23:00:43

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		计数器触发器逻辑集成电路光电二极管
页数	文件大小	规格书
10页	106K
描述
Synchronous 4-Bit Binary Counters

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DM74LS163AM 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SOP, SOP16,.25
针数：	16	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.5
Is Samacsys：	N	计数方向：	UP
系列：	LS	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e0	长度：	9.9 mm
负载/预设输入：	YES	逻辑集成电路类型：	BINARY COUNTER
最大频率@ Nom-Sup：	20000000 Hz	最大I（ol）：	0.008 A
工作模式：	SYNCHRONOUS	位数：	4
功能数量：	1	端子数量：	16
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	最大电源电流（ICC）：	32 mA
传播延迟（tpd）：	38 ns	认证状态：	Not Qualified
座面最大高度：	1.75 mm	子类别：	Counters
最大供电电压 (Vsup)：	5.25 V	最小供电电压 (Vsup)：	4.75 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	TTL	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	触发器类型：	POSITIVE EDGE
宽度：	3.9 mm	最小 fmax：	20 MHz
Base Number Matches：	1

DM74LS163AM 数据手册

August 1986

Revised April 2000

DM74LS161A • DM74LS163A

Synchronous 4-Bit Binary Counters

The carry look-ahead circuitry provides for cascading

counters for n-bit synchronous applications without addi-

tional gating. Instrumental in accomplishing this function

are two count-enable inputs and a ripple carry output.

General Description

These synchronous, presettable counters feature an inter-

nal carry look-ahead for application in high-speed counting

designs. The DM74LS161A and DM74LS163A are 4-bit

binary counters. The carry output is decoded by means of

a NOR gate, thus preventing spikes during the normal

counting mode of operation. Synchronous operation is pro-

vided by having all flip-flops clocked simultaneously so that

the outputs change coincident with each other when so

instructed by the count-enable inputs and internal gating.

This mode of operation eliminates the output counting

spikes which are normally associated with asynchronous

(ripple clock) counters. A buffered clock input triggers the

four flip-flops on the rising (positive-going) edge of the

clock input waveform.

Both count-enable inputs (P and T) must be HIGH to count,

and input T is fed forward to enable the ripple carry output.

The ripple carry output thus enabled will produce a high-

level output pulse with a duration approximately equal to

the high-level portion of the Q_Aoutput. This high-level over-

flow ripple carry pulse can be used to enable successive

cascaded stages. HIGH-to-LOW level transitions at the

enable P or T inputs may occur, regardless of the logic

level of the clock.

These counters feature a fully independent clock circuit.

Changes made to control inputs (enable P or T or load) that

will modify the operating mode have no effect until clocking

occurs. The function of the counter (whether enabled, dis-

abled, loading, or counting) will be dictated solely by the

conditions meeting the stable set-up and hold times.

These counters are fully programmable; that is, the outputs

may be preset to either level. As presetting is synchronous,

setting up a low level at the load input disables the counter

and causes the outputs to agree with the setup data after

the next clock pulse, regardless of the levels of the enable

input. The clear function for the DM74LS161A is asynchro-

nous; and a low level at the clear input sets all four of the

flip-flop outputs LOW, regardless of the levels of clock,

load, or enable inputs. The clear function for the

DM74LS163A is synchronous; and a low level at the clear

inputs sets all four of the flip-flop outputs LOW after the

next clock pulse, regardless of the levels of the enable

inputs. This synchronous clear allows the count length to

be modified easily, as decoding the maximum count

desired can be accomplished with one external NAND

gate. The gate output is connected to the clear input to

synchronously clear the counter to all low outputs.

Features

■ Synchronously programmable

■ Internal look-ahead for fast counting

■ Carry output for n-bit cascading

■ Synchronous counting

■ Load control line

■ Diode-clamped inputs

■ Typical propagation time, clock to Q output 14 ns

■ Typical clock frequency 32 MHz

■ Typical power dissipation 93 mW

Ordering Code:

Order Number Package Number

Package Description

DM74LS161AM

DM74LS161AN

DM74LS163AM

DM74LS163AN

M16A

N16E

M16A

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

DS006397

www.fairchildsemi.com

12 3 4 5 6 7...10

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DM74LS163AM 替代型号

型号	品牌	替代类型	描述	数据表
SN74LS163ANSRE4	TI	功能相似	Synchronous 4-Bit Binary Counters 16-SO 0 to 70

与DM74LS163AM相关器件

型号	品牌	获取价格	描述	数据表
DM74LS163AMX	FAIRCHILD	获取价格	Synchronous Up Counter
DM74LS163AN	FAIRCHILD	获取价格	Synchronous 4-Bit Binary Counters
DM74LS163AN	NSC	获取价格	Synchronous 4-Bit Binary Counters
DM74LS163AN/A+	ETC	获取价格	Synchronous Up Counter
DM74LS163AN/B+	ETC	获取价格	Synchronous Up Counter
DM74LS163AW	NSC	获取价格	Synchronous 4-Bit Binary Counters
DM74LS163J	NSC	获取价格	IC,COUNTER,UP,4-BIT BINARY,LS-TTL,DIP,16PIN,CERAMIC
DM74LS163J/A+	ETC	获取价格	Synchronous Up Counter
DM74LS163N	NSC	获取价格	IC,COUNTER,UP,4-BIT BINARY,LS-TTL,DIP,16PIN,PLASTIC
DM74LS163N/A+	ETC	获取价格	Synchronous Up Counter

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