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DM74AS533WM PDF预览

DM74AS533WM

更新时间: 2024-10-01 04:53:59
品牌 Logo 应用领域
美国国家半导体 - NSC 总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
4页 115K
描述
Octal D-Type Transparent Latch with TRI-STATE Outputs

DM74AS533WM 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:0.300 INCH, PLASTIC, SOP-20Reach Compliance Code:unknown
风险等级:5.92Is Samacsys:N
系列:ASJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):100 mA
传播延迟(tpd):8 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

DM74AS533WM 数据手册

 浏览型号DM74AS533WM的Datasheet PDF文件第2页浏览型号DM74AS533WM的Datasheet PDF文件第3页浏览型号DM74AS533WM的Datasheet PDF文件第4页 
December 1989  
DM74AS533 Octal D-Type Transparent  
Latch with TRI-STATE Outputs  
É
General Description  
These 8-bit registers feature totem-pole TRI-STATE outputs  
designed specifically for driving highly-capacitive or relative-  
ly low-impedance loads. The high-impedance state and in-  
creased high-logic-level drive provide these registers with  
the capability of being connected directly to and driving the  
bus lines in a bus-organized system without need for inter-  
face or pull-up components. They are particularly attractive  
for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
levels) or a high-impedance state. In the high-impedance  
state the outputs neither load nor drive the bus lines signifi-  
cantly.  
The output control does not affect the internal operation of  
the latches. That is, the old data can be retained or new  
data can be entered even while the outputs are off.  
Features  
Y
Switching specifications at 50 pF  
The eight inverting latches of the AS533 are transparent D-  
type latches, meaning that while the enable (G) is high the Q  
outputs will follow the complement of the data (D) inputs.  
When the enable is taken low the output will be latched at  
the complement of the level of the data that was set up.  
Y
Switching specifications guaranteed over full tempera-  
range  
ture and V  
CC  
Y
Y
Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
TRI-STATE buffer-type outputs drive bus lines directly  
A buffered output control input can be used to place the  
eight outputs in either a normal logic state (high or low logic  
Connection Diagram  
Dual-In-Line Package  
TL/F/6311–1  
Order Number DM74AS533WM or DM74AS533N  
See NS Package Number M20B or N20A  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/6311  
RRD-B30M105/Printed in U. S. A.  

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