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DM74AS574WM PDF预览

DM74AS574WM

更新时间: 2024-11-14 22:39:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 63K
描述
Octal D-Type Edge-Triggered Flip-Flops with 3-STATE Outputs

DM74AS574WM 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.300 INCH, MS-013, SOIC-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.38
Is Samacsys:N系列:AS
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:80000000 Hz
最大I(ol):0.048 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:9 ns
传播延迟(tpd):9 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.5 mmBase Number Matches:1

DM74AS574WM 数据手册

 浏览型号DM74AS574WM的Datasheet PDF文件第2页浏览型号DM74AS574WM的Datasheet PDF文件第3页浏览型号DM74AS574WM的Datasheet PDF文件第4页浏览型号DM74AS574WM的Datasheet PDF文件第5页浏览型号DM74AS574WM的Datasheet PDF文件第6页 
October 1986  
Revised March 2000  
DM74AS574  
Octal D-Type Edge-Triggered Flip-Flops  
with 3-STATE Outputs  
General Description  
Features  
Switching specifications at 50 pF  
These 8-bit registers feature totem-pole 3-STATE outputs  
designed specifically for driving highly-capacitive or rela-  
tively low-impedance loads. The high-impedance state and  
increased HIGH-logic-level drive provide these registers  
with the capability of being connected directly to and driv-  
ing the bus lines in a bus-organized system without need  
for interface or pull-up components. They are particularly  
attractive for implementing buffer registers, I/O ports, bidi-  
rectional bus drivers, and working registers.  
Switching specifications guaranteed over full tempera-  
ture and VCC range  
Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
Functionally equivalent with DM74S374  
Improved AC performance over DM74S374 at approxi-  
mately half the power  
The eight flip-flops of the DM74AS574 are edge-triggered  
D-type flip-flops. On the positive transition of the clock, the  
Q outputs will be set to the logic states that were set up at  
the D inputs.  
3-STATE buffer-type outputs drive bus lines directly  
Bus structured pinout  
A buffered output control input can be used to place the  
eight outputs in either a normal logic state (HIGH or LOW  
logic levels) or a high impedance state. In the high-imped-  
ance state the outputs neither load nor drive the bus lines  
significantly.  
The output control does not affect the internal operation of  
the flip-flops. That is, the old data can be retained or new  
data can be entered even while the outputs are OFF.  
The pinout is arranged to ease printed circuit board layout.  
All data inputs are on one side of the package while all the  
outputs are on the other side.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74AS574WM  
DM74AS574N  
M20B  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
© 2000 Fairchild Semiconductor Corporation  
DS006314  
www.fairchildsemi.com  

DM74AS574WM 替代型号

型号 品牌 替代类型 描述 数据表
SN74AS574DW TI

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