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DM74AS286M_NL

更新时间： 2024-11-15 21:06:51
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 光电二极管逻辑集成电路
页数 文件大小 规格书
7页 282K
描述
Parity Generator/Checker, AS Series, 9-Bit, True Output, TTL, PDSO14, 0.150 INCH, LEAD FREE, MS-120, SOIC-14

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DM74AS286M_NL 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.59其他特性：EVEN PARITY GENERATOR; ODD/EVEN PARITY CHECKER
系列：ASJESD-30 代码：R-PDSO-G14
JESD-609代码：e3/e4长度：8.65 mm
逻辑集成电路类型：PARITY GENERATOR/CHECKER位数：9
功能数量：1端子数量：14
最高工作温度：70 °C最低工作温度：
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE传播延迟（tpd）：15 ns
认证状态：Not Qualified座面最大高度：1.75 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：COMMERCIAL
端子面层：MATTE TIN/NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：3.9 mmBase Number Matches：1

DM74AS286M_NL 数据手册

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June 2007  
DM74AS286  
tm  
9-Bit Parity Generator/Checker with Bus-Driver  
Parity I/O Port  
Features  
General Description  
■ PNP inputs to reduce bus loading  
These universal, 9-bit parity generators/checkers utilize  
advanced Schottky high performance circuitry and fea-  
ture odd/even outputs to facilitate operation of either odd  
or even parity applications. The word length capability is  
easily expanded by cascading.  
■ Generates either odd or even parity for nine data lines  
■ Inputs are buffered to lower the drive requirements  
■ Can be used to upgrade existing systems using MSI  
parity circuits  
The DM74AS286 can be used to upgrade the perfor-  
mance of most systems utilizing the DM74AS280 parity  
generator/checker. Although the DM74AS286 is imple-  
mented without expander inputs, the corresponding  
function is provided by the availability of an input pin  
XMIT. XMIT is a control line which makes parity error  
output active and parity an input port when HIGH; when  
LOW, parity error output is inactive and parity becomes  
an output port. In addition, parity I/O control circuitry  
contains a feature to keep the I/O port in the 3-STATE  
during power UP or DOWN to prevent bus glitches.  
■ Cascadable for n-bits  
■ Switching specifications at 50pF  
■ Switching specifications guaranteed over full  
temperature and V range  
CC  
■ A parity I/O portable to drive bus  
Ordering Information  
Order  
Number  
Package  
Number  
Package Description  
DM74AS286M  
M14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering number.  
Function Table  
Connection Diagram  
Number of  
Parity I/O  
Inputs (A thru I)  
Parity Mode of  
that are HIGH Input Output XMIT Error Operation  
0, 2, 4, 6, 8  
1, 3, 5, 7, 9  
0, 2, 4, 6, 8  
0, 2, 4, 6, 8  
1, 3, 5, 7, 9  
1, 3, 5, 7, 9  
N/A  
N/A  
H
H
L
L
H
H
H
L
Parity  
Generator  
L
N/A  
N/A  
N/A  
N/A  
H
H
H
H
Parity  
Checker  
L
H
L
Parity  
Checker  
L
H
L = LOW Logic Level  
H = HIGH Logic Level  
N/A = Not Applicable  
©1986 Fairchild Semiconductor Corporation  
DM74AS286 Rev. 1.2  
www.fairchildsemi.com  
1234567

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DM74AS286MA+ TI

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 		AS SERIES, 9-BIT PARITY GENERATOR/CHECKER, TRUE OUTPUT, PDSO14, 0.150 INCH, PLASTIC, SOP-1
DM74AS286MA+X TI

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 		AS SERIES, 9-BIT PARITY GENERATOR/CHECKER, TRUE OUTPUT, PDSO14, 0.150 INCH, PLASTIC, SOP-1
DM74AS286MX FAIRCHILD

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DM74AS286MX TI

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 		AS SERIES, 9-BIT PARITY GENERATOR/CHECKER, TRUE OUTPUT, PDSO14, 0.150 INCH, PLASTIC, SOP-1
DM74AS286N FAIRCHILD

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 		9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port
DM74AS286N/A+ ETC

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 		Parity Generator/Checker
DM74AS286N/B+ ETC

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 		Parity Generator/Checker
DM74AS30 FAIRCHILD

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 		8 Input NAND Gate
DM74AS30J TI

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 		IC,LOGIC GATE,8-INPUT NAND,AS-TTL,DIP,14PIN,CERAMIC
DM74AS30J/A+ ETC

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