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DM74AS30N PDF预览

DM74AS30N

更新时间: 2024-11-14 22:56:51
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
4页 49K
描述
8 Input NAND Gate

DM74AS30N 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:DIP包装说明:PLASTIC, DIP-14
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.51
Is Samacsys:N系列:AS
JESD-30 代码:R-PDIP-T14JESD-609代码:e3
长度:19.18 mm逻辑集成电路类型:NAND GATE
最大I(ol):0.02 A功能数量:1
输入次数:8端子数量:14
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT APPLICABLE
电源:5 V最大电源电流(ICC):4.9 mA
Prop。Delay @ Nom-Sup:5 ns传播延迟(tpd):4.5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:5.08 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT APPLICABLE宽度:7.62 mm
Base Number Matches:1

DM74AS30N 数据手册

 浏览型号DM74AS30N的Datasheet PDF文件第2页浏览型号DM74AS30N的Datasheet PDF文件第3页浏览型号DM74AS30N的Datasheet PDF文件第4页 
April 1984  
Revised March 2000  
DM74AS30  
8 Input NAND Gate  
General Description  
This device contains a single gate which performs the logic  
Features  
Switching specifications at 50 pF  
NAND function.  
Switching specifications guaranteed over full tempera-  
ture and VCC range  
Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
Functionally and pin for pin compatible with Schottky,  
low power Schottky, and advanced low power Schottky  
TTL counterpart  
Improved AC performance over Schottky, low power  
Schottky, and advanced low power Schottky counter-  
parts  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74AS30M  
DM74AS30N  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Y = ABCDEFGH  
Inputs  
Output  
A thru H  
All inputs H  
One or More  
Inputs L  
Y
L
H
H = HIGH Logic Level  
L = LOW Logic Level  
© 2000 Fairchild Semiconductor Corporation  
DS006279  
www.fairchildsemi.com  

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