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DM74AS32M PDF预览

DM74AS32M

更新时间: 2024-11-14 22:39:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 63K
描述
Quad 2-Input OR Gate

DM74AS32M 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.46
Is Samacsys:N系列:AS
JESD-30 代码:R-PDSO-G14JESD-609代码:e3
长度:8.65 mm逻辑集成电路类型:OR GATE
最大I(ol):0.02 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):26.6 mAProp。Delay @ Nom-Sup:5.8 ns
传播延迟(tpd):5.8 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.75 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

DM74AS32M 数据手册

 浏览型号DM74AS32M的Datasheet PDF文件第2页浏览型号DM74AS32M的Datasheet PDF文件第3页浏览型号DM74AS32M的Datasheet PDF文件第4页浏览型号DM74AS32M的Datasheet PDF文件第5页 
April 1984  
Revised March 2000  
DM74AS32  
Quad 2-Input OR Gate  
General Description  
This device contains four independent gates, each of which  
Features  
Switching specifications at 50 pF  
performs the logic OR function.  
Switching specifications guaranteed over full  
temperature and VCC range  
Advanced oxide-isolated, ion-implanted  
Schottky TTL process  
Functionally and pin for pin compatible with Schottky,  
low power Schottky, and advanced low power Schottky  
TTL counterpart  
Improved AC performance over Schottky, low power  
Schottky and advanced low power Schottky counter-  
parts  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74AS32M  
DM74AS32SJ  
DM74AS32N  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Y = A + B  
Inputs  
Output  
A
L
B
L
Y
L
L
H
L
H
H
H
H
H
H
H = HIGH Logic Level  
L = LOW Logic Level  
© 2000 Fairchild Semiconductor Corporation  
DS006280  
www.fairchildsemi.com  

DM74AS32M 替代型号

型号 品牌 替代类型 描述 数据表
SN74AS32DR TI

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SN74AS32D TI

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