Datasheet > DM2202T1-15I

DM2202T1-15I

更新时间： 2024-02-28 16:53:54

品牌	Logo	应用领域
铁电 - RAMTRON		动态存储器光电二极管内存集成电路
页数	文件大小	规格书
19页	156K
描述
Cache DRAM, 1MX4, 15ns, CMOS, PDSO44

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中文翻译

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技术参数
数据手册

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DM2202T1-15I 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	TSOP2
包装说明：	TSOP, TSOP44,.36,32	针数：	44
Reach Compliance Code：	unknown	风险等级：	5.8
Is Samacsys：	N	最长访问时间：	15 ns
I/O 类型：	COMMON	JESD-30 代码：	R-PDSO-G44
JESD-609代码：	e0	内存密度：	4194304 bit
内存集成电路类型：	CACHE DRAM	内存宽度：	4
端子数量：	44	字数：	1048576 words
字数代码：	1000000	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	1MX4
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP	封装等效代码：	TSOP44,.36,32
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：	240	电源：	3.3 V
认证状态：	Not Qualified	刷新周期：	1024
自我刷新：	NO	最大待机电流：	0.001 A
子类别：	DRAMs	最大压摆率：	0.18 mA
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

DM2202T1-15I 数据手册

are not allowed because a DRAM refresh cycle does not occur when

a read refresh address matches the LRR address latch.

/CAL — Column Address Latch

This input is used to latch the column address and in combination

with /WE to trigger write operations. When /CAL is high, the column

address latch is transparent. When /CAL is low, the column address

latch is closed and the output of the latch contains the address

present while /CAL was high.

Initialization Cycles

A minimum of 10 initialization (start-up) cycles are required

before normal operation is guaranteed. At least eight /F refresh

cycles and two read cycles to different row addresses are necessary

to complete initialization. /RE must be high for at least 300ns prior

to initialization.

W/R — Write/Read

This input along with /F specifies the type of DRAM operation

initiated on the low going edge of /RE. When /F is high, W/R

specifies either a write (logic high) or read operation (logic low).

Unallowed Mode

Read, write, or /RE only refresh operations must not be

performed to unselected memory banks by clocking /RE when /S is

high.

/F — Refresh

This input will initiate a DRAM refresh operation using the

internal refresh counter as an address source when it is low on the

low going edge of /RE.

Reduced Pin Count Operation

Although it is desirable to use all EDRAM control pins to

/WE — Write Enable

optimize system performance, it is possible to simplify the interface

to the EDRAM by either tying pins to ground or by tying one or

more control inputs together. The /S input can be tied to ground if

the low power standby modes are not required. The /CAL and /F

pins can be tied together if hidden refresh operation is not

required. In this case, a CBR refresh (/CAL before /RE) can be

performed by holding the combined input low prior to /RE. A CBR

refresh does not require that a row address be supplied when /RE

is asserted. The timing is identical to /F refresh cycle timing. The

/WE input can be tied to /CAL if independent posting of column

addresses and data are not required during write operations. In

this case, both column address and write data will be latched by

the combined input during writes. W/R and /G can be tied together

if reads are not performed during write hit cycles. If these

techniques are used, the EDRAM will require only three control

lines for operation (/RE, /CAS [combined /CAL, /F, and /WE], and

W/R [combined W/R and /G]). The simplified control interface still

allows the fast page read/write cycle times, fast random read/write

times, and hidden precharge functions available with the EDRAM.

This input controls the latching of write data on the input data

pins. A write operation is initiated when both /CAL and /WE are low.

/G — Output Enable

This input controls the gating of read data to the output data

pins during read operations.

/S — Chip Select

This input is used to power up the I/O and clock circuitry.

When /S is high, the EDRAM remains in its low power mode. /S

must remain active throughout any read or write operation. With

the exception of /F refresh cycles, /RE should never be clocked

when /S is inactive.

DQ — Data Input/Output

0-3

These bidirectional data pins are used to read and write data

to the EDRAM. On the DM2212 write-per-bit memory, these pins

are also used to specify the bit mask used during write operations.

_0-10— Multiplex Address

These inputs are used to specify the row and column

addresses of the EDRAM data. The 11-bit row address is latched on

the falling edge of /RE. The 9-bit column address can be specified

at any other time to select read data from the SRAM cache or to

specify the write column address during write cycles.

Pin Descriptions

/RE — Row Enable

This input is used to initiate DRAM read and write operations

and latch a row address. It is not necessary to clock /RE to read

data from the EDRAM SRAM row registers. On read operations, /RE

can be brought high as soon as data is loaded into cache to allow

early precharge.

V Power Supply

^CCThese inputs are connected to the +5 or +3.3 volt power supply.

V Ground

These inputs are connected to the power supply ground

connection.

Pin Names

Function

Pin Names

Function

Address Inputs

Row Enable

Ground

0-10

/WE

Write Enable

Output Enable

Refresh Control

/RE

Data In/Data Out

0-3

/CAL

W/R

Column Address Latch

Write/Read Control

Power (+5V or +3.3V)

Chip Select - Active/Standby Control

Not Connected

1-22

1 2 345 6 7...19

中文翻译

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与DM2202T1-15I相关器件

型号	品牌	获取价格	描述	数据表
DM2202T1-15L	ETC	获取价格	Enhanced DRAM (EDRAM)
DM2202T-12	RAMTRON	获取价格	Cache DRAM, 1MX4, 12ns, CMOS, PDSO44
DM2202T-12I	CYPRESS	获取价格	Cache DRAM, 1MX4, 12ns, CMOS, PDSO44,
DM2202T-12L	RAMTRON	获取价格	Cache DRAM, 1MX4, 12ns, CMOS, PDSO44,
DM2202T-15	RAMTRON	获取价格	Cache DRAM, 1MX4, 35ns, MOS, PDSO44, 0.300 INCH, PLASTIC, TSOP2-44
DM2202T-15I	ETC	获取价格	Enhanced DRAM (EDRAM)
DM2202T-15L	ETC	获取价格	Enhanced DRAM (EDRAM)
DM2203T-12	ETC	获取价格	Enhanced DRAM (EDRAM)
DM2203T-12I	ETC	获取价格	Enhanced DRAM (EDRAM)
DM2203T-15	ETC	获取价格	Enhanced DRAM (EDRAM)

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