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DM2212J1-12I PDF预览

DM2212J1-12I

更新时间： 2024-01-18 07:40:13
品牌 Logo 应用领域
铁电 - RAMTRON 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
19页 156K
描述
Cache DRAM, 1MX4, 30ns, MOS, PDSO28, 0.300 INCH, PLASTIC, SO-28

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DM2212J1-12I 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete包装说明：SOJ, SOJ28,.34
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.02风险等级：5.92
Is Samacsys：N访问模式：FAST PAGE/STATIC COLUMN
最长访问时间：30 ns其他特性：RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH; 512 X 4 SRAM
I/O 类型：COMMONJESD-30 代码：R-PDSO-J28
JESD-609代码：e0内存密度：4194304 bit
内存集成电路类型：CACHE DRAM内存宽度：4
功能数量：1端口数量：1
端子数量：28字数：1048576 words
字数代码：1000000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX4输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：SOJ
封装等效代码：SOJ28,.34封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
刷新周期：1024自我刷新：NO
最大待机电流：0.001 A子类别：DRAMs
最大压摆率：0.225 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：MOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

DM2212J1-12I 数据手册

 浏览型号DM2212J1-12I的Datasheet PDF文件第2页浏览型号DM2212J1-12I的Datasheet PDF文件第3页浏览型号DM2212J1-12I的Datasheet PDF文件第4页浏览型号DM2212J1-12I的Datasheet PDF文件第5页浏览型号DM2212J1-12I的Datasheet PDF文件第6页浏览型号DM2212J1-12I的Datasheet PDF文件第7页 
DM2202/2212 EDRAM  
1Mb x 4 Enhanced Dynamic RAM  
Product Specification  
Enhanced  
Memory Systems Inc.  
Features  
■ 2Kbit SRAM Cache Memory for 12ns Random Reads Within a Page ■ Hidden Precharge and Refresh Cycles  
■ Fast 4Mbit DRAM Array for 30ns Access to Any New Page  
■ Write Posting Register for 12ns Random Writes and Burst Writes  
Within a Page (Hit or Miss)  
■ 256-byte Wide DRAM to SRAM Bus for 14.2 Gigabytes/Sec Cache  
Fill  
■ On-chip Cache Hit/Miss Comparators Maintain Cache Coherency  
on Writes  
■ Write-per-bit Option (DM2212) for Parity and Video Applications  
■ Extended 64ms Refresh Period for Low Standby Power  
■ 300 Mil Plastic SOJ and TSOP-II Package Options  
■ +5 and +3.3 Volt Power Supply Voltage Options  
■ Low Power, Self Refresh Mode Option  
■ Industrial Temperature Range Option  
Description  
Architecture  
The 4Mb Enhanced DRAM (EDRAM) combines raw speed with  
The EDRAM architecture has a simple integrated SRAM cache  
innovative architecture to offer the optimum cost-performance solution which allows it to operate much like a page mode or static column  
for high performance local or system main memory. In most high  
speed applications, no-wait-state performance can be achieved without  
DRAM.  
The EDRAM’s SRAM cache is integrated into the DRAM array as  
secondary SRAM cache and without interleaving main memory banks at tightly coupled row registers. Memory reads always occur from the  
system clock speeds through 50MHz. Two-way interleave will allow no- cache row register. When the internal comparator detects a page hit,  
wait-state operation at clock speeds greater than 100MHz without the  
only the SRAM is accessed and data is available in 12ns from column  
need of secondary SRAM cache. The EDRAM outperforms conventional address. When a page read miss is detected, the new DRAM row is  
SRAM cache plus DRAM memory systems by minimizing processor wait loaded into the cache and data is available at the output all within  
states for all possible bus events, not just cache hits. The combination 30ns from row enable. Subsequent reads within the page (burst reads  
of data and address latching, 2K of fast on-chip SRAM cache, and  
simplified on-chip cache control allows system level flexibility,  
or random reads) can continue at 12ns cycle time. Since reads occur  
from the SRAM cache, the DRAM precharge can occur simultaneously  
performance, and overall memory cost reduction not available with any without degrading performance. The on-chip refresh counter with  
other high density memory component. Architectural similarity with  
JEDEC DRAMs allows a single memory controller design to support  
either slow JEDEC DRAMs or high speed EDRAMs. A system designed in  
this manner can provide a simple upgrade path to higher system  
performance.  
independent refresh bus allows the EDRAM to be refreshed during  
cache reads.  
Memory writes are internally posted in 12ns and directed to the  
DRAM array. During a write hit, the on-chip address comparator  
activates a parallel write path to the SRAM cache to maintain  
TSOP-II Pin  
Configuration  
SOJ Pin  
Configuration  
Functional Diagram  
NC  
1
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
V
SS *  
A
Column  
Add  
Latch  
0-8  
/CAL  
A
0
2
V
SS  
Column Decoder  
NC  
3
V
SS  
512 X 4 Cache (Row Register)  
A
1
4
DQ  
0
11 Bit  
Comp  
NC  
5
DQ  
1
A
V
SS  
1
2
3
4
5
6
7
28  
27  
26  
25  
0
A
3
6
DQ  
2
A
Sense Amps  
& Column Write Select  
DQ  
0
1
/G  
A
4
7
NC  
DQ  
A
DQ  
1
3
I/O  
Control  
and  
Data  
Latches  
NC  
8
3
Last  
Row  
Read  
Add  
A
DQ  
2
4
A
A
5
9
/G  
V
0-10  
DQ  
0-3  
A
DQ  
3
24  
5
/RE  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
CC  
/RE  
23 /G  
V
V
CC  
Latch  
CC  
/S  
V
V
CC  
22  
21  
20  
19  
18  
CC  
V
V
SS  
SS  
V
V
SS  
8
SS  
Memory  
Array  
(2048 X 512 X 4)  
Row  
Add  
Latch  
V
V
SS  
SS  
A
6
9
/WE  
/WE  
/S  
A
6
/WE  
/S  
A
7
10  
11  
12  
13  
14  
A
7
A
8
/F  
A
8
/F  
A
2
17 W/R  
NC  
NC  
W/R  
NC  
/CAL  
A
9
16  
15  
/CAL  
A
2
V
V
A
CC  
CC  
10  
NC  
A
0-9  
V
SS  
/F  
W/R  
/RE  
Row Add  
and  
Refresh  
Control  
A
9
Refresh  
Counter  
V
A
CC  
10  
V
NC  
CC*  
* Reserved for future use  
© 1996 Enhanced Memory Systems Inc., 1850 Ramtron Drive, Colorado Springs, CO  
Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced  
80921  
38-2107-002  
The information contained herein is subject to change without notice.  
Enhanced reserves the right to change or discontinue this product without notice.  
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与DM2212J1-12I相关器件

型号 品牌 描述 获取价格 数据表
DM2212J1-12L RAMTRON Cache DRAM, 1MX4, 30ns, MOS, PDSO28, 0.300 INCH, PLASTIC, SO-28

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DM2212J1-15 RAMTRON Cache DRAM, 1MX4, 15ns, CMOS, PDSO28

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DM2212J1-15I RAMTRON Cache DRAM, 1MX4, 15ns, CMOS, PDSO28

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DM2212J1-15L ETC Enhanced DRAM (EDRAM)

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DM2212J-12 ETC Enhanced DRAM (EDRAM)

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DM2212J-12I ETC Enhanced DRAM (EDRAM)

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