DM1M36SJ6/DM1M32SJ6 Multibank EDO
1Mbx36/1Mbx32 Enhanced DRAM
SIMM
Enhanced
Memory Systems Inc.
Product Specification
Features
Architecture
The DM1M36SJ achieves
■ 8KByte SRAM Cache Memory for 12ns Random Reads Within Four
Active Pages (Multibank Cache)
■ Fast DRAM Array for 30ns Access to Any New Page
■ Write Posting Register for 12ns Random Writes and Burst Writes
Within a Page (Hit or Miss)
1Mb x 36 density by mounting
nine 1Mb x 4 EDRAMs,
packaged in 28-pin plastic
SOJ packages, on a multi-
layer substrate. Eight DM2242
■
■
2KByte Wide DRAM to SRAM Bus for 113.6 Gigabytes/Sec Cache Fill
On-chip Cache Hit/Miss Comparators Maintain Cache Coherency on Writes
devices and one DM2252
device provide data and parity
■ Hidden Precharge and Refresh Cycles
storage. The DM1M32SJ6
■ Extended 64ms Refresh Period for Low Standby Power
contains eight DM2242
■
Standard CMOS/TTL Compatible I/O Levels and +5 or 3.3V Volt Supply
devices for data only.
■ Compatibility with JEDEC 1M x 36 DRAM SIMM Configuration
The EDRAM memory
Allows Performance Upgrade in System
Multibank Extended Data Output (EDO) for Faster System Operation
module architecture is very
■
similar to a standard 4MB
■ Low Power, Self Refresh Option
■ Industrial Temperature Range Option
DRAM module with the
addition of an integrated
cache and on-chip control
Description
which allows it to operate much like an EDO DRAM.
The EDRAM’s SRAM cache is integrated into the DRAM array as
tightly coupled row registers. The EDRAM has a total of four
independent DRAM memory banks each with its own SRAM row
register. Memory reads always occur from the cache row register of
one of these banks as specified by row address bits A and A (bank
select). When the internal comparator detects that the row address
matches the last row read from any of the four DRAM banks (page
hit), the SRAM is accessed and data is available on the output pins in
12ns from the column address input. Subsequent reads within the
page (burst reads or random reads) can continue at 12ns cycle time.
When the row address does not match the last row read from any of
the last four DRAM banks (page miss), the new DRAM row is
accessed and loaded into the appropriate SRAM row register and data
is available on the output pins all within 30ns from row enable.
Subsequent reads within the page (burst reads or random reads) can
continue at 12ns cycle time.
The Enhanced Memory Systems Multibank EDO 4MB EDRAM
SIMM module provides a single memory module solution for the
main memory or local memory of fast PCs, workstations, servers, and
other high performance systems. Due to its fast 12ns cache row
register, the EDRAM memory module supports zero-wait-state burst
read operations at up to 83MHz bus rates in a non-interleave
configuration and 132MHz bus rates with a two-way interleave configuration.
On-chip write posting and fast page mode operation supports
12ns write and burst write operations. On a cache miss, the fast
DRAM array reloads the 2KByte cache over a 2KByte-wide bus in 18ns
for an effective bandwidth of 113.6 Gbytes/sec. This means very low
latency and fewer wait states on a cache miss than a non-integrated
cache/DRAM solution. The JEDEC compatible 72-bit SIMM
2
9
configuration allows a single memory controller to be designed to
support either JEDEC slow DRAMs or high speed EDRAMs to provide
a simple upgrade path to higher system performance.
Since reads occur from the SRAM
cache, the DRAM precharge can occur
Functional Diagram
during burst reads. This eliminates the
A
0-8
Column
Add
Latch
precharge time delay suffered by other
/CAL
0-3,P
Column Decoder
DRAMs and SDRAMs when accessing a
4-512 X 36 Cache Pages
(Row Registers)
new page. The EDRAM has an
11-Bit
Comp
independent on-chip refresh counter and
dedicated refresh control pin to allow the
Sense Amps
& Column Write Select
/G
DRAM array to be refreshed concurrently
I/O
Last
Row
Read
Add
Control
and
Data
A
with cache read operations (hidden
0-10
DQ
/S
0-35
refresh).
Latches
Latch
Memory writes are posted to the
data latch and directed to the DRAM
array. During a write hit, the on-chip
address comparator activates a parallel
write path to the SRAM cache to maintain
coherency. Random or page mode writes
can be posted 5ns after column address
Memory
Array
2048 x 512 x 36
Row
Add
Latch
/WE
V
CC
A
0-9
C
1-9
/F
Row Add
and
Refresh
Control
V
SS
Refresh
Counter
W/R
/RE
0,2
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product without notice.
© 1996 Enhanced Memory Systems Inc. 1850 Ramtron Drive, Colorado Springs, CO
Telephone (800) 545-DRAM, Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced
80921
38-2118-000
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