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DEI1148-QMS-G PDF预览

DEI1148-QMS-G

更新时间: 2024-11-06 02:52:19
品牌 Logo 应用领域
DEIAZ 信息通信管理接口集成电路
页数 文件大小 规格书
8页 532K
描述
OCTAL ARINC 429 LINE RECEIVER

DEI1148-QMS-G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:MQFP-44针数:44
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.52
其他特性:ALSO OPERATE WITH 5V SUPPLY差分输出:NO
输入特性:DIFFERENTIAL SCHMITT TRIGGER接口集成电路类型:LINE RECEIVER
接口标准:ARINC 429JESD-30 代码:S-PQFP-G44
JESD-609代码:e3长度:10 mm
湿度敏感等级:3功能数量:8
端子数量:44最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK峰值回流温度(摄氏度):260
认证状态:Not Qualified最大接收延迟:200 ns
接收器位数:8座面最大高度:2.45 mm
最大供电电压:3.63 V最小供电电压:2.97 V
标称供电电压:3.3 V电源电压1-最大:5.5 V
电源电压1-分钟:4.5 V电源电压1-Nom:5 V
表面贴装:YES技术:BICMOS
温度等级:MILITARY端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:10 mmBase Number Matches:1

DEI1148-QMS-G 数据手册

 浏览型号DEI1148-QMS-G的Datasheet PDF文件第2页浏览型号DEI1148-QMS-G的Datasheet PDF文件第3页浏览型号DEI1148-QMS-G的Datasheet PDF文件第4页浏览型号DEI1148-QMS-G的Datasheet PDF文件第5页浏览型号DEI1148-QMS-G的Datasheet PDF文件第6页浏览型号DEI1148-QMS-G的Datasheet PDF文件第7页 
Device  
Engineering  
Incorporated  
DEI1148  
OCTAL ARINC 429 LINE  
RECEIVER  
385 East Alamo Drive  
Chandler, AZ 85225  
Phone: (480) 303-0822  
Fax: (480) 303-0824  
E-mail: admin@deiaz.com  
FEATURES  
·
·
·
Octal ARINC 429 to TTL/CMOS logic line receivers  
Operates from single +5 V ± 10% or 3.3 V ± 10% power supply  
Operates in high noise environment  
o
o
Input Common Voltage Range: ± 20 V  
2 V minimum Input hysteresis  
·
·
·
ARINC inputs internally protected to lightning requirements of DO-160 Level A3  
Withstands inadvertent short to 115 Vac on inputs  
Package: 44L MQFP, 13.9mm footprint  
PINOUT  
PIN  
NAME  
DESCRIPTION  
429 INPUTS. ARINC 429 format serial  
digital data “A” inputs.  
15, 13, 11, 9,  
2, 44, 42, 40  
IN[8:1]A  
429 INPUTS. ARINC 429 format serial  
digital data “B” inputs.  
16, 14, 12, 10,  
3, 1, 43, 41  
IN[8:1]B  
TESTAA  
LOGIC INPUT. Test input A (+) for odd  
channels.  
5
6
7
8
LOGIC INPUT. Test input A (-) for odd  
channels.  
TESTAB  
LOGIC INPUT. Test input B (+) for even  
channels.  
TESTBA  
LOGIC INPUT. Test input B (-) for even  
channels.  
TESTBB  
LOGIC OUTPUTS. CMOS/TTL format  
serial digital data “A” outputs.  
19, 21, 23, 25,  
32, 34, 36, 38  
OUT[8:1]A  
OUT[8:1]B  
LOGIC OUTPUTS. CMOS/TTL format  
serial digital data “B” outputs.  
18, 20, 22, 24,  
31, 33, 35, 37  
29  
27  
VDD  
VSS  
POWER INPUT. 5 V OR 3.3 V.  
POWER INPUT. Ground.  
Figure 1 DEI1148 Pinout  
©2019 Device Engineering Inc.  
Page 1 of 8  
DS-MW-01148-01 Rev B  
01/08/2019  

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