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DEI1167-TES-G PDF预览

DEI1167-TES-G

更新时间: 2024-11-06 02:52:27
品牌 Logo 应用领域
DEIAZ 输入元件信息通信管理光电二极管输出元件接口集成电路
页数 文件大小 规格书
8页 91K
描述
OCTAL GND/OPEN INPUT PARALLEL OUTPUT INTERFACE IC

DEI1167-TES-G 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.68
接口集成电路类型:INTERFACE CIRCUITJESD-30 代码:R-PDSO-G24
JESD-609代码:e4长度:7.7978 mm
湿度敏感等级:2功能数量:1
端子数量:24封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
座面最大高度:1.1938 mm最大供电电压:3.63 V
最小供电电压:2.97 V标称供电电压:3.3 V
电源电压1-最大:5.5 V电源电压1-分钟:4.5 V
电源电压1-Nom:5 V表面贴装:YES
技术:BICMOS端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:4.3942 mmBase Number Matches:1

DEI1167-TES-G 数据手册

 浏览型号DEI1167-TES-G的Datasheet PDF文件第2页浏览型号DEI1167-TES-G的Datasheet PDF文件第3页浏览型号DEI1167-TES-G的Datasheet PDF文件第4页浏览型号DEI1167-TES-G的Datasheet PDF文件第5页浏览型号DEI1167-TES-G的Datasheet PDF文件第6页浏览型号DEI1167-TES-G的Datasheet PDF文件第7页 
Device  
Engineering  
Incorporated  
DEI1167  
OCTAL GND/OPEN INPUT,  
PARALLEL OUTPUT INTERFACE IC  
385 E. Alamo Dr.  
Chandler, AZ 85225  
Phone: (480) 303-0822  
Fax: (480) 303-0824  
E-mail: admin@deiaz.com  
FEATURES  
x
Eight GND/OPEN discrete inputs  
o
o
o
o
o
Meet electrical requirements for ABD0100 GND/OPEN discrete input.  
Hysteresis provides noise immunity.  
Internal pull up resistor  
Internal isolation diode  
Inputs protected from Lightning Induced Transients per DO160D, Section 22, Cat A3 and B3.  
x
3.3V or 5V TTL/CMOS compatible digital IO  
o
o
8 tri-state outputs  
/CS & /OE control inputs  
x
x
x
Logic Supply:  
Analog Supply:  
24L TSSOP package  
3.3V or 5V  
12V  
PIN ASSIGNMENTS  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
DO1  
DO2  
GND  
DO3  
DO4  
VCC  
DO5  
DO6  
DO7  
DO8  
GND  
VDD  
DIN1  
DIN2  
DIN3  
DIN4  
DIN5  
DIN6  
DIN7  
DIN8  
NC  
DEI1167  
Figure 1 DEI1167 Pin Assignment  
(24 Lead TSSOP)  
9
16  
15  
14  
13  
10  
11  
12  
NC  
/CS  
/OE  
Table 1 Pin Descriptions  
Pins  
Name  
Description  
8-1  
DIN[8:1]  
Discrete Inputs. Eight Ground/Open format discrete signals. These have an internal pull-  
up to VDD. The threshold and hysteresis characteristics are determined by the applied  
VDD voltage.  
9-10  
11  
12  
NC  
/CS  
/OE  
Not Connected.  
Chip Select Logic Input. Low input selects the device. Internal pull-up to VCC.  
Output Enable Logic Input. Low input when /CS is low will enable the tri-state outputs.  
Internal pull-up to VCC.  
13  
14  
VDD  
GND  
Analog Supply. +12V  
Analog Ground.  
19  
22  
VCC  
GND  
Logic Supply. +3.3V or +5V  
Logic Ground.  
15-18,20,21,23,24  
DO[8:1]  
Logic Outputs. Eight tri-state data outputs.  
©2015 Device Engineering Inc  
Page 1 of 8  
DS-MW-01167-01 Rev B  
02/17/2015  

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