Device
Engineering
Incorporated
DEI1167
OCTAL GND/OPEN INPUT,
PARALLEL OUTPUT INTERFACE IC
385 E. Alamo Dr.
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
FEATURES
x
Eight GND/OPEN discrete inputs
o
o
o
o
o
Meet electrical requirements for ABD0100 GND/OPEN discrete input.
Hysteresis provides noise immunity.
Internal pull up resistor
Internal isolation diode
Inputs protected from Lightning Induced Transients per DO160D, Section 22, Cat A3 and B3.
x
3.3V or 5V TTL/CMOS compatible digital IO
o
o
8 tri-state outputs
/CS & /OE control inputs
x
x
x
Logic Supply:
Analog Supply:
24L TSSOP package
3.3V or 5V
12V
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DO1
DO2
GND
DO3
DO4
VCC
DO5
DO6
DO7
DO8
GND
VDD
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
NC
DEI1167
Figure 1 DEI1167 Pin Assignment
(24 Lead TSSOP)
9
16
15
14
13
10
11
12
NC
/CS
/OE
Table 1 Pin Descriptions
Pins
Name
Description
8-1
DIN[8:1]
Discrete Inputs. Eight Ground/Open format discrete signals. These have an internal pull-
up to VDD. The threshold and hysteresis characteristics are determined by the applied
VDD voltage.
9-10
11
12
NC
/CS
/OE
Not Connected.
Chip Select Logic Input. Low input selects the device. Internal pull-up to VCC.
Output Enable Logic Input. Low input when /CS is low will enable the tri-state outputs.
Internal pull-up to VCC.
13
14
VDD
GND
Analog Supply. +12V
Analog Ground.
19
22
VCC
GND
Logic Supply. +3.3V or +5V
Logic Ground.
15-18,20,21,23,24
DO[8:1]
Logic Outputs. Eight tri-state data outputs.
©2015 Device Engineering Inc
Page 1 of 8
DS-MW-01167-01 Rev B
02/17/2015