Datasheet > DEI1167-TMS-G

DEI1167-TMS-G

更新时间： 2022-06-24 15:42:04

品牌	Logo	应用领域
DEIAZ		输入元件输出元件
页数	文件大小	规格书
8页	91K
描述
OCTAL GND/OPEN INPUT PARALLEL OUTPUT INTERFACE IC

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DEI1167-TMS-G 数据手册

DIN[8:1] INPUT STRUCTURE

Refer to Figure 2. Each DINn signal is conditioned by the resistor / diode network and presented to the comparator IN+. The

reference and hysteresis voltage is developed at the comparator IN-. Notable features:

When Vdd is +12V, the circuit shall source ~0.9mA to a grounded input. This current will prevent a “dry” relay

contact.

The input threshold voltage and hysteresis with Vdd = 12V ±10%:

The falling Vth > 3.5V

The rising Vth < 7.5V

Hysteresis > 1.5V

The comparator includes an RC filter to provide noise rejection of transient pulses of up to several us. Thus there is a

relatively large DINx setup time of several us (Refer to timing parameter tsu2).

The inputs can withstand continuous input voltages of 40V minimum. The isolation diode breakdown voltage is

greater than 50V. The 12K Ohm input resistor is designed to limit diode breakdown current to safe levels during

transient events.

TIMING DIAGRAMS

7.5

INPUT

3.5

t_HL

1.5

OUTPUT

C_L= 30pF

Figure 3 Input to Output Delay

3.0

OE or CE

1.5

t_ZL

t_HZ

t_LZ

t_ZH

HIGH Z

0.2

1.3

OUTPUT

0.2

HIGH Z

V_IN= V_SS

R_L= 1K: to V_SS

C_L= 30pF

V_IN= V_DD

R_L= 1K: to V_CC

C_L= 30pF

Figure 4 Chip Select or Output Enable to Output Delay

Page 3 of 8

DS-MW-01167-01 Rev B

02/17/2015

1 234 5 6 7 8

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