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DEI1028-SES-G PDF预览

DEI1028-SES-G

更新时间: 2024-09-16 01:14:55
品牌 Logo 应用领域
DEIAZ /
页数 文件大小 规格书
7页 126K
描述
Voltage Clamping Circuit

DEI1028-SES-G 数据手册

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Device  
Engineering  
Incorporated  
DEI1028  
Voltage Clamping  
Circuit  
385 East Alamo Drive  
Chandler, AZ 85225  
Phone: (480) 303-0822  
Fax: (480) 303-0824  
E-mail: admin@deiaz.com  
FEATURES  
x
Protection for power electronics on 28VDC avionics or industrial power bus to  
DO-160, Category Z, Abnormal Surge Voltage (DC) levels.  
Controls power P-FET to clamp transient at 34V.  
Small foot print (8L SOIC NB).  
Wide input voltage range.  
Programmable Undervoltage Lockout.  
Logic compatible On/Off input.  
x
x
x
x
x
x
x
Stable over temperature.  
Soft start delay.  
GENERAL DESCRIPTION  
The DEI1028 is a control circuit for a 28VDC power bus voltage clamp. It is designed for use as the front end to a 28VDC  
input power supply to provide transient voltage protection. It controls the gate drive of a P-Channel power MOSFET to  
linearly clamp the output during over-voltage transients. The output voltage is maintained below the clamping threshold of  
35V (max) which is adequate to protect most Commercial-Off-The-Shelf switching supplies, linear regulators, and op  
amps.  
There is an Undervoltage Lockout feature that shuts the Power MOSFET off when the input voltage is below a user  
programmed threshold. An open collector logic output annunciates the under-voltage status. There is also a logic on/off  
input which may be used to control the power circuit. An external capacitor may be used to set a delay from when input  
power is applied to when the MOSFET is turned on.  
Table 1 Pin Definitions  
Description  
Pin #  
Name  
Figure 1: Pin  
Diagram  
OUTPUT. Controls the gate of the external P-channel power  
MOSFET.  
1
GATE  
IN/OUT. Controls the soft start delay of the device. Use 0.22uF for  
200ms minimum soft start time.  
2
CAP  
3
4
5
IN  
INPUT. Power input for the DEI1028 Voltage Clamp.  
UVL  
NON  
INPUT. Controls the under voltage lockout condition of the device.  
INPUT. Logic low enables device. Logic high disables device.  
OUTPUT. Open collector output. Active low when IN is below UVL  
threshold.  
6
NUV  
7
8
GND  
OUT  
POWER. Ground  
INPUT. Feedback to gate control from drain of Power MOSFET.  
© 2017 Device Engineering Inc.  
Page 1 of 7  
DS-MW-01028-01-J  
April 14, 2017  

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