CYWB022XX Family
Document History Page
Document Title: CYWB022XX Family, West Bridge®: Astoria™ USB and Mass Storage Peripheral Controller
Document Number: 001-13805
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
866960 VSO / PSZ
See ECN New datasheet
*A
2208371
JYEE /
VSO
See ECN 1) Corrected the Pin name (R/B#) in Table 2, Updated I
to I
in Table 3,
SB1
SB3
Updated Table 5, Updated Figure 14 to Figure 18 (timing diagrams), In Table
6, moved “Interface Bandwidth” to first row, Updated Table 7, Updated Figure
22, Added Figure 23 (new), Updated Figure 24 to 26, Updated Table 8,
Updated Figure 27, Added Table 9 (Async SRAM mode Timing), Updated
Figure 29 - 31, Updated Table 10, Updated Figure 32 - 43, Updated Table 11,
Updated Table 12, Updated Figure 45, Updated Table 14, Added Table 16, and
21. Updated Figure 47.
2) Added two part numbers (CYWB0226ABS and CYWB0226ABM) in the title,
Modified Feature list (same as Astoria Advance Information), Updated
Features to include “Integrated USB Switch”, Updated Figure 1, Updated USB
Interface (U-Port), Added Figure 2, Updated section 3.6, Updated Table 2,
Updated Figure 14, Added Table 4, Updated Table 5-6, Updated Figure 15-19,
Updated Table 7, Updated Figure 20-21, Updated Table 8, Updated Figure
22-27, Updated Table 9, Update Figure 28-29, Updated Table 10, Updated
Figure 30-32, Updated Table 11, Updated Figure 33-54, Updated Table 12,
Updated Figure 55, Updated Table 13-14, Updated Figure 56-58, Updated
Table 15-16, Added Table 17-18, Updated Table 19, Updated Figure 59, and
Added two part numbers (CYWB0226ABS and CYWB0226ABM) in the order
information (section 9).
*B
2503171
VSO /
AESA
See ECN 1. “Features” - added 3.91x3.91 mm 81-ball WLCSP to Small footprint bullet.
2. “Processor Interface (P-Port)” - added “The P-Port of the WLCSP package
only supports PNAND and SPI interface” and “The 81-ball WLCSP package
only supports interrupt.”
3. “Clocking” - added “The 81-ball WLCSP only supports 19.2 and 26 MHz
external clock input.” and Tables 1 and 2
4. Table 4 - added the column of “Ball #”
5. Table 5 - added a new table for WLCSP pin assignment
6. Figure 13 - removed the grid line
7. Figure 14 - new ball map for WLCSP package
8. Table 14 - add 33ns for tRC and tWC timing for WLCSP package
9. Figure 55 - updated the SPI timing diagram
10. “Ordering Information” - added WLCSP package ordering code to the table
11. Add CYWB0224ABSX, CYWB0224ABMX CYWB0226ABSX,
CYWB0226ABMX.
*C
2521024
VSO /
AESA
See ECN 1. This version is final - Removed status “Preliminary”
2. Update the section of “Core Power Down Mode”
3. Note 3 of Table 6 has added the requirement of SSVDDQ and SNVDDQ in
SD/MMC modes
4. SNVDDQ in Table 6 added Note 3
5. Table 17, add parameter tWH
6. Figure 22 and Figure 27 have been updated
7. Table 18, add parameter tAVH
8. Figure 28 and Figure 29 have been updated
9. Table 20, the value of parameters “tPROG” and “tR” have been updated
10. Table 23, removed parameter of “tA”
11. Figure 58 I2C timing diagram has been updated
Document Number: 001-13805 Rev. *M
Page 76 of 78
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