Datasheet > CYWT16B512-133FZQB

CYWT16B512-133FZQB

更新时间： 2024-01-22 18:18:43

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英飞凌 - INFINEON		/
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CYWT16B512

512 Mb (64 MB), 3.0 V Serial NOR Flash

Memory

Wide temperature range

General description

The CY16B family devices are Flash non-volatile memory products using:

• Floating Gate technology

• 65 nm process lithography

The CY16B family connects to a host system via a serial peripheral interface (SPI). Traditional SPI serial input and

output (IO₁and IO₅) is supported and eight bit wide quad I/O (QIO) and quad peripheral interface (QPI)

commands. In addition, there are double data rate (DDR) read commands for QIO and QPI that transfer address

and read data on both edges of the clock.

The architecture features a Page Programming Buffer that allows up to 512-bytes to be programmed in one

operation and provides individual 8 KB sector, 64 KB half block, 128 KB block, or entire chip erase.

By using CY16B family devices at the higher clock rates supported, with Quad commands, the instruction read

transfer rate can match or exceed traditional parallel interface, asynchronous, NOR Flash memories, while

reducing signal count dramatically.

The CY16B family products offer high densities coupled with the flexibility and fast performance required by a

variety of mobile or embedded applications. Provides an ideal storage solution for systems with limited space,

signal connections, and power. These memories offer flexibility and performance well beyond ordinary serial

flash devices. They are ideal for code shadowing to RAM, executing code directly (XIP), and storing

re-programmable data.

Features

• SPI with multi-I/O

- Clock polarity and phase modes 0 and 3

- DDR option

- QPI option

- Extended addressing: 24- or 32-bit address options

- This device connects two Quad I/O SPI devices with two CS# resulting in an eight bit data I/O path

• Read

- Commands: Normal, fast, dual I/O, quad I/O, dualO, quadO, DDR quad I/O.

- Modes: Burst wrap, continuous (XIP), QPI

- Serial flash discoverable parameters (SFDP) for configuration information.

• Program architecture

- 512 bytes page programming buffer 3.0 V CYWT16B Flash memory

- Program suspend and resume

• Erase Architecture

- Uniform 8 KB sector erase

- Uniform 64 KB half block erase

- Uniform 128 KB block erase

- Chip erase

- Erase suspend and resume

• 100,000 program/erase cycles

• 20 year data retention

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 1 of 152

002-34691 Rev. **

2022-05-25

12 3 4 5 6 7...152

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