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CYWB0220ABSX2-FDXIT PDF预览

CYWB0220ABSX2-FDXIT

更新时间： 2024-01-01 08:38:57
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储控制器
页数 文件大小 规格书
78页 1534K
描述
West Bridge®: Astoria™ USB and Mass Storage Peripheral Controller

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CYWB0220ABSX2-FDXIT 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：VFBGA,Reach Compliance Code：compliant
HTS代码：8542.31.00.01风险等级：5.65
JESD-30 代码：R-PBGA-B81JESD-609代码：e1
长度：3.91 mm湿度敏感等级：3
端子数量：81最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
座面最大高度：0.55 mm最大供电电压：1.9 V
最小供电电压：1.7 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.4 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：3.907 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUIT
Base Number Matches：1

CYWB0220ABSX2-FDXIT 数据手册

 浏览型号CYWB0220ABSX2-FDXIT的Datasheet PDF文件第72页浏览型号CYWB0220ABSX2-FDXIT的Datasheet PDF文件第73页浏览型号CYWB0220ABSX2-FDXIT的Datasheet PDF文件第74页浏览型号CYWB0220ABSX2-FDXIT的Datasheet PDF文件第75页浏览型号CYWB0220ABSX2-FDXIT的Datasheet PDF文件第77页浏览型号CYWB0220ABSX2-FDXIT的Datasheet PDF文件第78页 
CYWB022XX Family  
Document History Page  
Document Title: CYWB022XX Family, West Bridge®: Astoria™ USB and Mass Storage Peripheral Controller  
Document Number: 001-13805  
Orig. of  
Change  
Submission  
Date  
Rev.  
ECN No.  
Description of Change  
**  
866960 VSO / PSZ  
See ECN New datasheet  
*A  
2208371  
JYEE /  
VSO  
See ECN 1) Corrected the Pin name (R/B#) in Table 2, Updated I  
to I  
in Table 3,  
SB1  
SB3  
Updated Table 5, Updated Figure 14 to Figure 18 (timing diagrams), In Table  
6, moved “Interface Bandwidth” to first row, Updated Table 7, Updated Figure  
22, Added Figure 23 (new), Updated Figure 24 to 26, Updated Table 8,  
Updated Figure 27, Added Table 9 (Async SRAM mode Timing), Updated  
Figure 29 - 31, Updated Table 10, Updated Figure 32 - 43, Updated Table 11,  
Updated Table 12, Updated Figure 45, Updated Table 14, Added Table 16, and  
21. Updated Figure 47.  
2) Added two part numbers (CYWB0226ABS and CYWB0226ABM) in the title,  
Modified Feature list (same as Astoria Advance Information), Updated  
Features to include “Integrated USB Switch”, Updated Figure 1, Updated USB  
Interface (U-Port), Added Figure 2, Updated section 3.6, Updated Table 2,  
Updated Figure 14, Added Table 4, Updated Table 5-6, Updated Figure 15-19,  
Updated Table 7, Updated Figure 20-21, Updated Table 8, Updated Figure  
22-27, Updated Table 9, Update Figure 28-29, Updated Table 10, Updated  
Figure 30-32, Updated Table 11, Updated Figure 33-54, Updated Table 12,  
Updated Figure 55, Updated Table 13-14, Updated Figure 56-58, Updated  
Table 15-16, Added Table 17-18, Updated Table 19, Updated Figure 59, and  
Added two part numbers (CYWB0226ABS and CYWB0226ABM) in the order  
information (section 9).  
*B  
2503171  
VSO /  
AESA  
See ECN 1. “Features” - added 3.91x3.91 mm 81-ball WLCSP to Small footprint bullet.  
2. “Processor Interface (P-Port)” - added “The P-Port of the WLCSP package  
only supports PNAND and SPI interface” and “The 81-ball WLCSP package  
only supports interrupt.”  
3. “Clocking” - added “The 81-ball WLCSP only supports 19.2 and 26 MHz  
external clock input.” and Tables 1 and 2  
4. Table 4 - added the column of “Ball #”  
5. Table 5 - added a new table for WLCSP pin assignment  
6. Figure 13 - removed the grid line  
7. Figure 14 - new ball map for WLCSP package  
8. Table 14 - add 33ns for tRC and tWC timing for WLCSP package  
9. Figure 55 - updated the SPI timing diagram  
10. “Ordering Information” - added WLCSP package ordering code to the table  
11. Add CYWB0224ABSX, CYWB0224ABMX CYWB0226ABSX,  
CYWB0226ABMX.  
*C  
2521024  
VSO /  
AESA  
See ECN 1. This version is final - Removed status “Preliminary”  
2. Update the section of “Core Power Down Mode”  
3. Note 3 of Table 6 has added the requirement of SSVDDQ and SNVDDQ in  
SD/MMC modes  
4. SNVDDQ in Table 6 added Note 3  
5. Table 17, add parameter tWH  
6. Figure 22 and Figure 27 have been updated  
7. Table 18, add parameter tAVH  
8. Figure 28 and Figure 29 have been updated  
9. Table 20, the value of parameters “tPROG” and “tR” have been updated  
10. Table 23, removed parameter of “tA”  
11. Figure 58 I2C timing diagram has been updated  
Document Number: 001-13805 Rev. *M  
Page 76 of 78  
1...737475767778

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