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CYWB0124AB-BVXI PDF预览

CYWB0124AB-BVXI

更新时间: 2024-11-18 09:46:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 362K
描述
West Bridge Antioch Memory-mapped interface to main processor

CYWB0124AB-BVXI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:VFBGA, BGA100,10X10,20Reach Compliance Code:compliant
ECCN代码:3A991.A.3HTS代码:8542.31.00.01
Factory Lead Time:1 week风险等级:8.38
JESD-30 代码:S-PBGA-B100JESD-609代码:e1
长度:6 mm湿度敏感等级:3
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装等效代码:BGA100,10X10,20
封装形状:SQUARE封装形式:GRID ARRAY, FINE PITCH
峰值回流温度(摄氏度):260电源:1.8,1.8/3.3 V
认证状态:Not Qualified座面最大高度:1 mm
子类别:Bus Controllers最大供电电压:1.9 V
最小供电电压:1.7 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:0.5 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:6 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUIT
Base Number Matches:1

CYWB0124AB-BVXI 数据手册

 浏览型号CYWB0124AB-BVXI的Datasheet PDF文件第2页浏览型号CYWB0124AB-BVXI的Datasheet PDF文件第3页浏览型号CYWB0124AB-BVXI的Datasheet PDF文件第4页浏览型号CYWB0124AB-BVXI的Datasheet PDF文件第5页浏览型号CYWB0124AB-BVXI的Datasheet PDF文件第6页浏览型号CYWB0124AB-BVXI的Datasheet PDF文件第7页 
ADVANCE  
INFORMATION  
CYWB012X Family  
West Bridge® Antioch™  
West Bridge® Antioch™  
Selectable clock input frequencies  
19.2 MHz, 24 MHz, 48 MHz  
Features  
SLIM® architecture, allowing simultaneous and independent  
data paths between processor and USB, and between USB  
and mass storage  
Expanded mass storage device support  
MMC/MMC+/SD  
CE-ATA for micro-HDD  
NAND Flash: × 8 or × 16, SLC  
Full NAND management (ECC, wear-leveling)  
High speed USB at 480 Mbps  
USB 2.0 compliant  
Integrated USB2.0 transceiver, smart Serial Interface Engine  
16 programmable endpoints  
Expanded selectable clock input frequencies  
19.2 MHz, 24 MHz, 26 MHz, 48 MHz  
Mass storage device support  
MMC/MMC+/SD  
NAND Flash: × 8 or × 16, SLC  
Full NAND management (ECC, wear-leveling)  
Applications  
Cellular Phones  
Portable Media Players  
Personal Digital Assistants  
Digital Cameras  
Memory-mapped interface to main processor  
DMA slave support  
Ultra low power, 1.8 V core operation  
Small footprint, 6 × 6 mm VFBGA and WLCSP  
Portable Video Recorder  
Logic Block Diagram  
West Bridge Antioch  
8051 MCU  
Control Registers  
Access Control  
P
U
SLIM
Mass Storage Interface  
SD/MMC/CE-ATA  
NAND  
S
Cypress Semiconductor Corporation  
Document #: 001-05898 Rev.*C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 14, 2011  
[+] Feedback  

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